uvm_rookie Posted August 4, 2011 Report Share Posted August 4, 2011 Is there a way to parameterize an UVM UVC ? The UVC is designed to have a MAX_LANES = 64. For a particular testbench, I want to configure this UVC to only has MAX_LANES=8. The following code doesn't work : class demo_tb extends uvm_env; `uvm_component_utils(demo_tb) bss_uvc_frmbuf_env #(.MAX_LANES(8)) frmbuf_env; function new (string name, uvm_component parent); super.new(name, parent); endfunction : new extern virtual function void build_phase(uvm_phase phase); endclass : demo_tb function void demo_tb::build_phase(uvm_phase phase); super.build_phase(phase); frmbuf_env = bss_uvc_frmbuf_env #(.MAX_LANES(8)) ::type_id::create("frmbuf_env", this); endfunction : build_phase I got the following error : ncelab: *E,TYCMPAT (./examples/demo_tb.sv,74|68): assignment operator type check failed (expecting datatype compatible with 'specialization of class bss_uvc_frmbuf_env' but found 'class bss_uvc_frmbuf_env' instead). ncelab: *F,CUPKGE: Elaboration cannot proceed: design unit 'demo_base_test' uses a SystemVerilog class 'demo_tb' for which an elaboration error occurred. Quote Link to comment Share on other sites More sharing options...
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