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Configuration visibility from virtual interface

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A virtual interface variable is used to reference an actual interface instance. Did you mean to ask how to access a configuration object from an interface instance? If so, then the answer is the same of any access of a configuration object outside of the UVM component hierarchy. You need to understand how the first two arguments to uvm_config_db#type)::get/set() are used to build a path name to select a configuration object. But before I spend more time explaining, it would help if you clarified your question. Also, what do you plan to do with this configuration object?

Edited by dave_59
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Hello Dave, thank you for the response. Sorry, yes, I meant to access a configuration object from an interface instance. I appreciate if you could elaborate how to access configuration object outside of UVM component. One use is to enable/disable check/assertions in interface. Another use is to pass configuration variables used in assertions.

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If you want to enable/disable checks in your UVM environment and have that propagate to the DUT through an interface then you can do that by having a virtual interface in your UVC that includes fields for checks_enable and coverage_enable. These could also be included in a config object. For simplicity I am showing an example where they are fields of the UVC.

The INTERFACE might have this:

interface apb_if (input pclock, input preset);
 bit                [b]has_checks[/b] = 1;
 bit                has_coverage = 1;

// PADDR must not be X or Z when PSEL is asserted
assertPAddrUnknown:assert property (
                 disable iff(![b]has_checks[/b])
                 (psel == 0 or !$isunknown(paddr)))
                   $error("ERR_APB001_PADDR_XZ\n PADDR went to X or Z \
                           when PSEL is asserted");
endinterface : apb_if

And the ENV might have this:

class apb_env extends uvm_env;

 protected virtual interface apb_if vif;  // Virtual Interface

 // Control checks and coverage in the bus monitor class and the interface.
 bit [b]checks_enable[/b] = 1;
 bit coverage_enable = 1;

 // Provide implementations of virtual methods such as get_type_name and create
 // Automate these fields so they are updated during the build_phase()
   `uvm_field_int([b]checks_enable[/b], UVM_DEFAULT)
   `uvm_field_int(coverage_enable, UVM_DEFAULT)

 extern virtual task run_phase(uvm_phase phase);
 extern virtual task update_vif_enables();

endclass : apb_env

// update_vif_enables
task apb_env::update_vif_enables();
 [b]vif.has_checks <= checks_enable;[/b]           // Set the enables at time 0
 vif.has_coverage <= coverage_enable;
 forever begin
   @([b]checks_enable [/b]|| coverage_enable);   // Reset if these signals are ever updated during sim
   [b]vif.has_checks <= checks_enable;[/b]
   vif.has_coverage <= coverage_enable;
endtask : update_vif_enables

task apb_env::run_phase(uvm_phase phase);
endtask : run_phase

So you can set the checks_enable to zero in the testbench, the test or via the command-line with this option:



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