one bug in uvm-1.1c library about uvm_reg

[mrforever]

Hi all

I think i have found one bug in uvm-1.1c library.

I am now using uvm_reg to verify the reg. There are two register sequences, which are seq_r1 and seq_r2.

code pieces in body() of seq_r1:

data = $urandom();

write_reg(model.R, status, data);

read_reg(model.R, status, rd_data);

if (rd_data != data) begin

...

end

code pieces in body() of seq_r2:

model.R.set(7);

update_reg(model.R, status);

mirror_reg(model.R, status, UVM_CHECK);

and the whole width of register R is 64 bits, the valid width of register R is 4 bits. the order of the sequence running is:

1) seq_r1

2) seq_r2

when i run the codes, vcs reports such a UVM_ERROR:

UVM_ERROR /EDA_Tools/synopsys/vcs_G-2012.09/etc/uvm-1.1/uvm-1.1c/src/reg/uvm_reg.svh(2884) @ 1432: reporter [RegModel] Register "model.R" value read from DUT (0x00000000cb7c2337) does not match mirrored value (0x0000000000000007)

0x00000000cb7c2337 which is generated by $urandom() is the value written to DUT.

when i change the desired value from 7 to 8 in seq_r2. the UVM_ERROR has disappeared.

I think that this may be one bug in uvm-1.1c library.

Did anybody run into similar problem? Please share with me. Thanks

Regards

mrforever

[mrforever]

I think that update_reg() should check not only the valid field value, but the whole value of register when it compares the desired value and mirrored value.