cliffc Posted February 23, 2013 Report Share Posted February 23, 2013 Hi, All - UVM uses a different phase-calling syntax than OVM. Examples: function void build_phase(uvm_phase phase); super.build_phase(phase); ... task run_phase (uvm_phase phase); ... I see the value of having "phase" with the run_phase(s) because I am going to do: phase.raise_objection(this); phase.drop_objection(this); But I am trying to understand why I would use this syntax with function-phases where I will not raise/drop objections. In fact, in the src/base/uvm_component.svh file, the code for the connect_phase() is the following: function void uvm_component::connect_phase(uvm_phase phase); connect(); return; endfunction So the function just appears to call the simpler-syntax connect() method. I had a student in UVM training that chose to use the simple names and the labs worked just fine. Only the final_phase() does not have a simpler OVM counterpart and there is also a final keyword in the SystemVerilog language. Any experts care to comment on the more complex calling syntax with no readily apparent value? Regards - Cliff Cummings www.sunburst-design.com Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.