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  1. I know that if I create a class ins after Line 30. like : test_reg_1 my_cast_reg; $cast(my_cast_reg, list[0]); This will sovle the issue, but I don't want to do this way.. because if I have 1000 sub-class of test_base.. I need to instance 1000 test_reg_xx , and based on maybe name or something else to implement 1000 $cast() ...it doesn't make sense to me. So how do you deal with these kind of issues?
  2. Hi All, I have an example to test my class extensions but something I don't understand clearly.. In below example, I push my extended class instance "TEST_REG_1" into "test_base" class queue. and simulation result shows that Line 33 is error .. So I think not really extended class instance is put into parent class queue. From the queue, I can still get parent class field "num", I can't access to child class field "test_reg_1". So who knows how to modify below codes to make it working? 1 2 3 4 class test_base; 5 int num = 1; 6 7 endclass 8 9 class test_reg_1 extends test_base; 10 int test_reg_1 = 1; 11 endclass 12 13 class test_reg_2 extends test_base; 14 int test_reg_2 = 1; 15 endclass 16 17 class test; 18 test_reg_1 TEST_REG_1; 19 test_reg_2 TEST_REG_2; 20 21 test_base list[$]; 22 23 function new(); 24 TEST_REG_1 = new(); 25 list.push_back(TEST_REG_1); 26 27 test_my_reg(); 28 endfunction 29 30 task test_my_reg(); 31 $display("num = %d", list[0].num); 32 33 $display("test_reg_1 = %d", list[0].test_reg_1); 34 endtask 35 36 endclass 37 38 program main; 39 40 test t ; 41 42 initial begin 43 t = new(); 44 end 45 46 endprogram Best wishes,
  3. Hi wilsony, I think you can't use create to put more arugments because in UVM source code, you can see that the arguments are defined in class uvm_object_registry. Maybe in your way, you can only use constructor "new" because you have more arguments than parent class. Anybody know the benefit to use create instead of new ?? typedef uvm_object_registry #(T) type_id; 229 // Function: create 230 // 231 // Returns an instance of the object type, ~T~, represented by this proxy, 232 // subject to any factory overrides based on the context provided by the 233 // ~parent~'s full name. The ~contxt~ argument, if supplied, supercedes the 234 // ~parent~'s context. The new instance will have the given leaf ~name~, 235 // if provided. 236 237 static function T create (string name="", uvm_component parent=null, 238 string contxt=""); 239 uvm_object obj; 240 uvm_factory f = uvm_factory::get(); 241 if (contxt == "" && parent != null) 242 contxt = parent.get_full_name(); 243 obj = f.create_object_by_type(get(),contxt,name); 244 if (!$cast(create, obj)) begin 245 string msg; 246 msg = {"Factory did not return an object of type '",type_name, 247 "'. A component of type '",obj == null ? "null" : obj.get_type_name(), 248 "' was returned instead. Name=",name," Parent=", 249 parent==null?"null":parent.get_type_name()," contxt=",contxt}; 250 uvm_report_fatal("FCTTYP", msg, UVM_NONE); 251 end 252 endfunction
  4. Hi Jadec, Thank you very much. Yes I set the UVM_VERBOSITY to highest in order to better understanding what's happenning. Best wishes,
  5. Hi cliffc, In UVM GOLDEN Reference Guide, Page 63, it is mentioned that "UVM provides an "objection" mechanism for this purpose. Other methods of stopping simulation, which were used in OVM and UVM-EA, such as calling global_stop_request, are deprecated in UVM. So in order to make it compatible to OVM, you should use the switch posted by dave_59, I think. Regards,
  6. I am new in UVM world When I print my topology in start_of_simulation, I see some information that I don't quite understand: [PHASESEQ] No default phase sequence for phase 'run/pre_reset/reset/post_reset/pre_configure/configure/post_configure/main/...." 1. Does it mean that I didn't set default sequence for my sequencer ? 2. Is there any problem if I don't set default sequence? 3. If I use "sequece.start(sequencer,xx,xx,xx)" in testcase , is it equal to set default sequence? Anybody can help my questions? Thanks a lot
  7. Hi uwes, I see the UVM example sometimes they implement raise/drop objection in run_phase() task of testcase which is derived from uvm_test class. what's the difference with the one you put raise_objectioin()/drop_objection() in pre_body() and post_body() of sequence classes ? the code is like this : task run_phase(uvm_phase phase); phase.raise_objection(this); seq.start(sqr, xxx); phase.drop_objection(this); endtask Is seq.start() a blocking function which would be released by sequencer ?? What's the consequence I don't use raise/drop in this run_phase() task ?
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