UVM Register Package

[neil]

Can anyone point me to a summary of what this package will provide?

I'd like the answer to be a single source file which allows the generation of consistent SystemVerilog address and field constants, the same for C, easy to browse designer documentation, and programming guide documentation. But maybe that's hoping for too much

Neil

[uwes]

hi,

the points you raise are outside of the scope of the UVM standard. The standard provides a defined set of sv base classes to model registers, memories, register fields, memory maps. they can be used in a testbench to simplify scenario creation or raise the abstraction level for easier checking/debug. saying that means also that the standard will NOT contain translation rules/references of other inputs formats such as ipxact files or generators to converts them into specialized SV classes.

however there are commercial providers (duolog for instance) of tools which can generate from a single source all data and documentation you are asking for AND also generate the specialized sv code for your register to integrate with the register package of UVM.

/uwe

[sri.cvcblr]

Can anyone point me to a summary of what this package will provide?

I'd like the answer to be a single source file which allows the generation of consistent SystemVerilog address and field constants, the same for C, easy to browse designer documentation, and programming guide documentation. But maybe that's hoping for too much

Neil

Neil,

As Uwe said that would be beyond the reg-pkg, but there are already tools that can do all what you have asked for. Checkout IDS/IVS from www.agnisys.com

Srini

www.cvcblr.com/blog

[neil]

Thanks Uwe, that's a helpful summary.

Neil

[jambabe]

Those things were intentionally left out of the UVM standard. But for what you're looking for, you can also look at what Semifore provides as a solution. They have a powerful cross-compiler which accepts register information in various input formats (IEEE 1685 IP-XACT, SystemRDL, RALF, etc), and it generates UVM register class definitions (not to mention OVM, VMM, IP-XACT, SystemRDL outupts).

semifore.com

[Discovery]

Hi I'm very new to verification, here I have few questions, doubts and some assumptions.

Kindly please help me to make obvious with below doubts and also correct me if I'm wrong in any of my assumption or definitions.

I have few questions with RALF and register package or register model file

Register package or model file - is a systemverilog file contains register and memory description classes.

I think the register model file generated using RALF file as inputs.

But still do we need both RALF and register model file during compilation and simulation or just register model file is enough ?

RALF is still needed after we generated the register model ?

The next doubt is,

Where the back door hdl_path constructs are used ?

Can a RALF file can have hdl_path option in the register description ?

My interest is to directly access the registers in DUT by specifying hierarchical path of the registers in the register description. And not to access via some bus protocol. So I think hdl_path could help for this situation.

My doubt is whether the hdl_path option can be created with RALF Register description or not ?

Or, Is the hdl_path options are only can be used in the register model file ?

My verification is based on the UVM.

One more doubt, Is the RALF file description and register model differ with the VMM or OVM or UVM ?

Please someone help!

Thanks in advance

Discovery