How to add a transparent sequence router?

[Logger]

I have ran into a couple of instances where it would be quite handy to introduce some form of sequence router into my environment. Basically, I have two drivers. I can execute a sequence on either one of them. But I'd like to add another sequencer in front of the two. It could have some routing rules (probably constraint based), such that I can run my sequence on this new router sequencer, and the router sequence will then execute the sequence on one of the two downstream sequencers.

I've tried building a virtual sequence to do this, but fields inside the sequence get populated once the virtual sequence starts executing. Passing the sequence to the downstream sequencers has undesirable side effects and doesn't seem to work.

Seems like we're missing a basic building block component, uvm_sequence_router.

-Ryan

[petermonsson]

Hi Ryan,

I don't see why the virtual sequence doesn't work. What do you mean with the fields get populated?

What kind of side effects would something like this have?

rand bit [2:0] m_rand_sqr;

task body();

seq = my_seq::type_id::create("seq");

seq.start(p_sequencer.my_sqr[m_rand_sqr]);

endtask

Best Regards

Peter