uvm skipping phase problem

[mrforever]

Hi, all

I am now meeting one problem when i use the option +UVM_PHASE_TRACE to run the test. It reports such UVM_INFOs.

UVM_INFO ../../../../uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1203) @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.main' (id=284) No objections raised, skipping phase

UVM_INFO ../../../../uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1203) @ 0: reporter [PH/TRC/SKIP] Phase 'uvm.uvm_sched.post_shutdown' (id=332) No objections raised, skipping phase

There are many similar UVM_INFOs and I list only two of them above. I dump the vpd file and see it with DVE, and observe that the simulation quits at 0 time point. I guess that there are no objections raised. But there are the codes starting_phase.raise_objection(this) in the pre_body() function and the codes starting_phase.drop_objection(this) in the post_body() function in the sequence already. Then I use the phase pane to debug. But it appears that there is no any active phase. Now I don't know how to debug it. Did any body meet such similar problem? Thanks for your help!

Regards

mrforever

Edited December 31, 2012 by mrforever

[mrforever]

Is there any expert in the forum now?

[IChip]

How do you run your sequence? Are you sure starting_phase is not a null handler?

[mrforever]

Hi,

How do you run your sequence? Are you sure starting_phase is not a null handler?

The codes is the same with the ubus example. List as follow:

// pre_body

virtual task pre_body();

if (starting_phase!=null) begin

`uvm_info(get_type_name(),

$sformatf("%s pre_body raising %s objection",

get_sequence_path(),

starting_phase.get_name()), UVM_MEDIUM);

starting_phase.raise_objection(this);

end

endtask: pre_body

// post body

virtual task post_body();

$display("Enter sequence's post_body!!!\n");

if (starting_phase!=null) begin

`uvm_info(get_type_name(),

$sformatf("%s post_body() dropping %s objection",

get_sequence_path(),

starting_phase.get_name()), UVM_MEDIUM);

starting_phase.drop_objection(this);

end

endtask : post_body

I also doubted that maybe starting_phase was null. But the architecture of the codes is the same with ubus example. Then I added the option +UVM_PHASE_TRACE in the file Makefile.vcs of ubus example. I found that there were the same UVM_INFOs like "No objections raised, skipping phase". And the ubus example can run successfully. I guess maybe it is not the true problem.

Regards

mrforver

Edited December 31, 2012 by mrforever

[mrforever]

Hi, all

It is running successfully when I changed the way of starting the sequence. I am now using seq.start(*.sequencer) explicitly to start the sequence. It used the way of setting the default sequence in test before and it didn't run successfully but quitted at 0 time point. I guess that the starting_phase may be null when using the way setting the default sequence to start the sequence sometimes. Maybe it's a bug in uvm. I don't know why? Did anybody run into the same problem?

[mastrick]

We use default_sequence and it works fine. The config_db can be particular, however. If your sequence is not starting at all (which sounds like the case), you can use the config_db tracing to see what is going on.

[mrforever]

We use default_sequence and it works fine. The config_db can be particular, however. If your sequence is not starting at all (which sounds like the case), you can use the config_db tracing to see what is going on.

Hi, mastrick

Thanks for your reply. Where is the config_db particularly? part of my codes in test are as follows:

virtual function void build_phase(uvm_phase phase);

env = chpp_env::type_id::create("env", this);

cfg_seq = chpp_config_sequence::type_id::create("cfg_seq", this);

begin

// Define the sequences to run in the run phase

uvm_config_db#(uvm_object_wrapper)::set(this,"*.env.cfg_agt.cfg_sqr.main_phase",

"default_sequence",

chpp_config_sequence::type_id::get());

end

// Create the tb

super.build_phase(phase);

endfunction : build_phase

[mastrick]

I think you want to remove the *. at the front of your "set" path, i.e.

uvm_config_db#(uvm_object_wrapper)::set(this,"env.cfg_agt.cfg_sqr.main_phase",

"default_sequence",

chpp_config_sequence::type_id::get());

as env is already in the context of "this". If that still does not work, turning on the config trace messages will show you what the sequencer is looking for when it queries for default_sequence in the uvm base layer.

[mrforever]

Hi mastrick,

thanks for your reply. I will try it.

Regards

mrforever

[uwes]

hi,

if you do instantiate your sequence manually then starting_sequence is unset(=null). if you use the show pre_body with the guard (starting_phase!=null) then raise_objection() it will not work since no objection is raised. typically i use the config-db with default_sequence and starting_phase.

/uwe