smallnokia Posted February 13, 2013 Report Share Posted February 13, 2013 I am new in UVM world When I print my topology in start_of_simulation, I see some information that I don't quite understand: [PHASESEQ] No default phase sequence for phase 'run/pre_reset/reset/post_reset/pre_configure/configure/post_configure/main/...." 1. Does it mean that I didn't set default sequence for my sequencer ? 2. Is there any problem if I don't set default sequence? 3. If I use "sequece.start(sequencer,xx,xx,xx)" in testcase , is it equal to set default sequence? Anybody can help my questions? Thanks a lot Quote Link to comment Share on other sites More sharing options...
jadec Posted February 13, 2013 Report Share Posted February 13, 2013 1. You may set a default sequence for each run-time phase. This message is generated for each phase that didn't find one. 2. No, the message is an info only (you've probably set UVM_VERBOSITY too high for normal usage). 3. It is similar but there are some differences. For example, the sequencer sets "starting_phase" variable in the sequence if it starts it as a default_sequence. Quote Link to comment Share on other sites More sharing options...
smallnokia Posted February 15, 2013 Author Report Share Posted February 15, 2013 Hi Jadec, Thank you very much. Yes I set the UVM_VERBOSITY to highest in order to better understanding what's happenning. Best wishes, 1. You may set a default sequence for each run-time phase. This message is generated for each phase that didn't find one. 2. No, the message is an info only (you've probably set UVM_VERBOSITY too high for normal usage). 3. It is similar but there are some differences. For example, the sequencer sets "starting_phase" variable in the sequence if it starts it as a default_sequence. Quote Link to comment Share on other sites More sharing options...
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