constraining sub-sequences in a virtual sequence - best practice?

[soloist_huaxin]

Say I have these sequences:

class cfg_seq extends uvm_sequence #(obj_type1);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

class item_seq extends uvm_sequence #(obj_type2);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

I want to use them in a virtual sequence like this:

class test_vseq extends uvm_sequence;
  `uvm_declare_p_sequencer(some_vseqr)
  `uvm_object_utils(test_vseq)

  rand int unsigned size_x;
  rand int unsigned size_y;

  rand cfg_seq cfg;
  rand item_seq item;

  //This is what I'm trying to achieve
  constraint size_c {
    cfg.size_x == this.size_x;
    cfg.size_y == this.size_y;
    item.size_x == this.size_x;
    item.size_y == this.size_y;
  }
...
  task body;
    `uvm_do_on(cfg, p_sequencer.cfg_seqr)
    `uvm_do_on(item, p_sequencer.item_seqr)
  endtask
endclass

What I'm trying to do is that I set "size_x" and "size_y" in test_vseq and have cfg and item pick it up from test_vseq, so I don't have to set them separately in config_db. What's the best way to do this?

 

[tudor.timi]

The way you have it set up now is that the size_c constraint is part of the test_vseq scope. This means it only applies when an instance of test_vseq gets randomized. The `uvm_do_on(...) macro includes a call to randomize() on the item/sequence you pass to it. This means the cfg sequence will get randomized without the size_c block. You have two choices here.

 

1. Use inline constraints:

`uvm_do_on_with(cfg, p_sequencer.cfg_seqr, { cfg.size_x == this.size_x, .... };

2. Randomize cfg in test_vseq's scope:

`uvm_create_on(cfg, p_sequencer.cfg_seqr)
if (!this.randomize(cfg))
  `uvm_fatal("RANDERR", "Randomization error");
`uvm_send(cfg)

The first method is less flexible in that you can't disable or extend the constraint in any way. It's hardcoded. For the second one, you can disable the size_c constraint when randomizing a test_vseq instance inline or you can overwrite it in a child class. For more info on the second method, have a look at my post on constraints from above.

[abbmir]

There is a third way. You can try using the "default_sequence" configuration parameter as a way to start sequences. 

 

    uvm_config_db#(uvm_object_wrapper)::set(this, "m_env.some_vseqr.run_phase",

          "default_sequence", test_vseq::type_id::get());

 

This is done in the build_phase of your uvm_test. This will randomize your virtual sequence and apply these constraints.