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wszhong631

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  1. hi, In uvm_phase file of uvm1.2, I understand that before_phase.m_successors.delete(after_phase) which is the 978th line code of add method should be 'before_phase.m_predecessors.delete(after_phase) ' , that is right ? 965 // IN BETWEEN 'BEFORE' and 'AFTER' PHASES 966 else if (before_phase != null && after_phase != null) begin 967 if (!after_phase.is_before(before_phase)) begin 968 `uvm_fatal("PH_ADD_PHASE",{"Phase '",before_phase.get_name(), 969 "' is not before phase '",after_phase.get_name(),"'"}) 970 end 971 // before
  2. thank you ,that is , when one user turn off automatic item recording , and if the user want to use register model to access some dut registers, that will be impossible.
  3. Hi, when I comile my testbench, automatic item recording has been turned off by defining UVM_DISABLE_AUTO_ITEM_RECORDING. a) set m_auto_item_recording to 0 in uvm_sequencer_base.svh, if call the function of is_auto_item_recording_enabled(),it return 0 `ifdef UVM_DISABLE_AUTO_ITEM_RECORDING local bit m_auto_item_recording = 0; `else local bit m_auto_item_recording = 1; `endif // Access to following internal methods provided via seq_item_export virtual function void disable_auto_item_recording(); m_auto_item_recording = 0; endfunction virtual function bit is_auto_item_re
  4. That is "DAP" access policy,you should add "+UVM_NO_DEPRECATED" option when you compile it .
  5. hi, when the register width differs from the bus width and one register access results in a series of bus transactions,such as using 32bit-width data bus can access 64-register dut by separated two times,this can be interrupted by grabed sequence,such as interrrupt sequence, A example of transaction_order may be A_upper( upper 32 bit of A register,suppose higher priority ) -----> Interrupt service sequence(may be access interrupt clear or mask register (two times ) -----> A_Lower( lower 32 bit of A register) whether the transaction order
  6. you must compile questasim_uvm_package.sv ,and vsim -uvmcontrol=all ,then add sequences to wave using UVM-Aware Debug windows, also,may add monitor transaction to wave using transaction record method , the version of mentor tools should 10.2b above. ,ple reference questa SIM user Mannal.
  7. Hi,I have such a question https://verificationacademy.com/forums/uvm/how-use-soft-constraint who can help me ? thanks /wszhong
  8. Hi! often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address. then , import the package into my test lib package, compile in order , test lib package is compiled lastly, but when compling code ,report macro address can't find? How to using package rightly in UVM? Large projects may have many packages with complex interdependencies,How to using it rightly ? thanks. /wszhong
  9. Hi! uvm_component_name_check_visitor This specialized visitor analyze the naming of the current component. The established rule set ensures that a component.get_full_name() is parsable, unique, printable to order to avoid any ambiguities when messages are being emitted. ruleset a legal name is composed of allowed charset “A-z:_0-9[](){}-: “ whitespace-as-is, no-balancing delimiter semantic, no escape sequences path delimiter not allowed anywhere in the name whether the name abc:_[] is legal or not ?how to use it?
  10. hi, I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that 1) trans_item is toper level sequence item(transaction layer item); 2) link_item is lower level sequence item(ie,link layer item); patial code as follows: class trans_item extends uvm_sequence_item; rand bit [31:0] mess_data[]; rand bit [15:0] mess_len; constraint C_mess{ soft mess_data.size()==mess_len;
  11. sorry,payloadseqment is a mis-spelling error when written this question. in sequence_item.svh, rand [7:0] payloadsegment[]; // payloadsegment that payload of some packets https://verificationacademy.com/forums/uvm/why-payloadsegment0-not-legal-c-identifier-namebut-payloadseqment0 Dave_59 says as follows "This warning is generated by Questa's built-in UVM-aware debug facilities. In order to use the debugging tools, the UVM created paths need the ability to be parsed by the command line. All vendor tools have this problem. You can ignore these warnings if you do not plan to us
  12. in order to watch UVM_details windows in questasim10.2c/10.2b,vlog option + questa_uvm_pkg options. Makefile as follows: questa_uvm_pkg=/app/mentor/questasim_10.2c/questasim/verilog_src/ vlog +incdir+$(uvm_home)/src $(uvm_home)/src/uvm.sv \ +incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv ............... under of simulation,report warning as follows: questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(364) @4080840000: reporter [iLLEGALNAME] 'payloadsegment[0]' is not a legal c identifier name.change to questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_re
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