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About desperado

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    Junior Member
  • Birthday 06/16/1984
  1. Hi All, I have a requirement to build an UVM Scoreboard, where the environment contains a single master and multi-slave data tx/rx protocol. Simple Working Operation: 1. Master is the one who initiates the Tx packet. 2. Based on the packet received the required slave sends the response Rx packet and so does the process goes on. Requirement: 1. I need to build a scoreboard where, the scoreboard will be getting information (i.e. Expected packet & Obtained packet from the master side) and so does the same at the slave side. 2. I have planned up to do a three level checks, which Includes: a. Tx packet integrity (i.e. whether right packet is generated or not) sent at the Master side. b. Tx packet integrity (i.e. whether the slave de-packetize the received packet properly and stored the information in fifo properly or not) received at the slave side. c. End to end packet which is been transmitted from the master to the slave. Idea's poped for verifying: 1. I had planned up to create an array of analysis fifo's connected to the scoreboard based on the number of components (i.e. 1 Master and N slaves). 2. Would be having three different functions/tasks or logic's which performs the above mentioned checks in Point 2 and do the same. Contradiction: 1. If I have multiple analysis ports, then based on the no of ports used, I should used different named write functions which might sometimes mess up stuffs. Poped-up Idea: 1. Can I used different subscribes inside the scoreboard based on the no of components required i.e. 1 subscriber for one master and N subscriber for N slaves etc inside the UVM scoreboard. Request: I would request if anyone gives me a much better idea/procedure for designing this scoreboard which verifies the data coming from master and multi-slave. Thanks in advance. Fresh Breath of UVM when started again !! Desperado: Passive -> Active State
  2. Hi Uwes, Thanks for what you had put up, but my doubt was when would the actual relase of UVM1.0 will happen, as it has been postponed for quite a long time. Thanks & Regards, Desperado -> Thanks to all for your polite replies :-)
  3. Hi All, I wish its quite a long time people are waiting around to have a peep into UVM1.0 as its been kept on postponed. Wish as per the above reply, can we expect that UVM1.0 would be release by 16th Feb of 2011 ?? . Any officials from Accellera or Mentor or Synopys or Cadence Can you say, would it be released on the above mentioned date ?? And one request its better to edit the roadmap of uvm1.0 as its been put up on the site, because its way too different & its out of time to market, and so does its mis-leading people around looking for this release. Thanks, Desperado --> Eyes kept still wide open to have a look into the UVM1.0
  4. Hi Accellera, Mentor, Synopsys, Cadence !! Was waiting with eye poped on 27th dec 2010, so called the release date for the UVM 1.0 as mentioned in the thread, but still things are not out. Can any officials comment on the same as we are waiting eagerly to see it. Thanks, Desperado --> ":o Eyes still wide open to see UVM 1.0 "
  5. Hi All, So as per the above note from "Adam Sherer" we can expect the UVM 1.0 release on the Accellera site by tomorrow i.e. Dec 27th 2010. I wish they release this time on time. Waiting for your release Accellera, wish there wont be any disappointments. Thanks, Desperado -> "Eyes Wide Open to look into UVM 1.0 dam eagerly"
  6. Hi All, Doubt is connect a VHDL DUT With an SV Interface!!! This is first declaration of a signal in vhdl like below:: type t_ar7_0 is array (natural range<>) of std_logic_vector(7 downto 0); This they have used to create a packed dimensional in vhdl for a port signal in the top module as given below:: ABC_MMM : out t_ar7_0(1 to 8); So its like 7 to 0 of 1 to 8 signal in vhdl... Now I had declared a counter part in interface to connect this module as logic [1:8] [7:0] abc_mmm; Now, in a module how to connect these two signals,, I tried like this but its giving illegal port connect for VHDL type. // DUT instance ABC abc_dut (.ABC_MMM(interface.abc_mmm)); How can i Connect a sort of array port declaration in VHDL with SV interface!!! Quite urgent help out plz.. Thanks, Desperado
  7. Hi UVM Accellera Team, As per the road map which you had given in the UVM world site, the UVM 1.0 Package would be release by October 30, 2010, but there are "no signs" of release or talks regarding the same. Basically you are "OUT of TIME TO MARKET". Can you let us out when would the package will be released, any specific/tentative date when we could see the UVM 1.0 released. Thanks, Desperado --> "Keen to have a look on UVM 1.0"
  8. Hi uwes, As an engineer, I am pretty curious on what's happen even behind the screen and so does was my question on this forum. Can you elaborate to my questions plz. Thanks, Desperado
  9. Hi All, A small clarification, where does memory gets created for the following process. Because memory are basically into stack , heap memory. --> For object allocation the tool is going to use the heap memory. --> For initialized variables and static variables the tool is going to use the stack memory. --> For recursive functions and re-entrant task what type of memory is been used by the tool?? Kindly let me know the same and as well correct me if I am wrong. Thanks, Desperado --> "Basics always important for mighty works"
  10. Hi All, I came across this domain of PSOC [Programmable System-On-Chip] in recent articles. How does it going to play a role in this SOC market and Would like to know in shot how is the future of PSOC. Thanks in Advance, Desperado --> "PSOC" --> Its Future in SOC Market???
  11. Hi Erling, Yes your are right, basically inside an uvm component you can use only one write function. But if you try to use more than one it might mess up. You can have a look at this link given below, basically this show some of the usage to overcome this problem. This basically was used in OVM, so does can be used for UVM as well. http://ovmworld.org/forums/showthread.php?877-Connecting-OVM-Monitor-with-OVM-Scoreboard!!-Wish-would-be-helpfull-for-people-!!&highlight=write+function+inside+scoreboard Kindly let know if you face any issue regarding the same. Thanks, Desperado --> A New Fresh Breath of "UVM" - Nice to feel this united "Air"
  12. Hi Adiel, Adam, Srini, Thanks to all of you for your active reply on the same. Its quite clear as of now. Thanks, Desperado -> Gud to hear that UVM is grooming behind the screens :-)
  13. @Adiel & Srini: Thanks to both of you for giving your inputs regarding the same. But well my intrusion was, what register package are they gona standardize inside UVM, as we RAL seems more popularized than other register package !!! Well are there any chance for knowing which register package are they going to use in UVM!!! Thanks For your reply, Desperado
  14. Hi All, Does VMM RAL exists in UVM as its been voted as the most used register package among all!! Or which one are they gona incorporate inside UVM ?? Kindly let me know its been decided. Thanks, Desperado -> "Unity In Diversity - "UVM"
  15. Hi Veeramuthu, Think already Questa will be supporting bcoz its there OVM base class modified into this UVM BCL, so ultimately they will support full UVM capability!! and so do the Cadence!! Since for one of our OVM TB we gave a run converted to UVM and it was running fine with Questa!! Nor sure with Synopsys VCS whether they support this UVM EA1, but soon they will be too as this is a combination of the Gaints :-) Thanks, Desperado --> --> -->
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