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Showing results for tags 'raise_objection'.
T or F: Objections should not be used in the uvm phases which are functions (i.e. build_phase, connect_phase, check_phase, ...). If True, why?
Hi All, I have a question regarding the proper placement of the following code for raising an objection in a multi-layered testbench (i.e. virtual sequencer -> virtual sub sequencer -> sub sequencer): <start snip> virtual task pre_start(); if(starting_phase != null) starting_phase.raise_objection(get_sequencer()); endtask <end snip> I have tested the physical sequences and they work when no virtual sequences are involved. With that isolated, I introduced the 2 virtual sequences and since the new default_sequence is the top virtual sequence, I placed a raise_objection there. Here is a summary of my trial runs: 1) Pure physical sequence as default_sequence - raise_objection at physical sequence (works); 2) Top virtual sequnce as default_sequence - raise_objection added to virtual sequence's pre_start (does not work); What happens to 2) is the top virtual sequence does not end but the sub sequences do not run either. Please shed some light on why this is happening and possible ways to fix this. Thanks, Martin