jlnagel Posted December 18, 2014 Report Share Posted December 18, 2014 Here is another question from an UVM beginner... I am designing/experimenting a simple setup comprising a component environment which includes a bus agent, a register model, etc. I added a configuration for the bus agent, which gets the configuration from the environment. Now the component itself needs a user-defined configuration, which I want to randomize. This configuration (describing the topology) will be passed e.g. to the register model. But in the top level testbench, I need to pass actual parameters (that were randomized) from this configuration. My questions: * can I do this pre-build randomization of the topology-related attributes with a component configuration ? We might expect that the parameter actual shall be constant, so that it is not possible to randomize them. * if its possible, from a methodology point of view, where should I then declare the configuration and how should the top level testbench and the top level environment share it ? Or: when using the uvm_config_db, who should set it and who should get it ? My first guess was that since it is recommended to pass configurations from top to bottom, I would naturally set the configuration in the top level tb. * if its not possible, what is then the appropriate methodology to randomize the parameter actuals of the DUT ? All this is not so clear for a beginner... Thank you in advance ! Quote Link to comment Share on other sites More sharing options...
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