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Component model access from both DUT and predictor

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I have a (VHDL) DUT which is a state machine that needs to talk to a peripheral, which we have a model for.


Our predictor (SystemC) also needs to access the peripheral model.  So we have two components which need access to a single model.


If the peripheral model is VHDL, I would let the DUT communicate with the peripheral model, and use a monitor hanging off the interface to synchronize to my predictor.


If the peripheral model is SystemC, I would let the predictor (which is also SystemC) talk directly to the model, and send a copy of the transaction to a FIFO in a synchronization component plugged in to the peripheral interface of the DUT.


Is this a typical scenario?  I've gotten both of these scenarios to work, I just wonder if there is a better way.



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