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SystemC Language

1,297 topics in this forum

  1. Is there any way to initialize input port in module?The problem occurs in reset function when i initialize readdata32_16 port.

    By fayz,
    • 4 replies
    • 358 views

  2. setup of systemC

    By fayz,
    • 1 reply
    • 393 views

  3. Questions about SystemC simulation time

    By YYF,
    • 4 replies
    • 640 views

  4. What is the difference between set_data_length() and set_streaming_width() in tlm_generic_payload

    By Ramarao V,
    • 7 replies
    • 1.9k views

  5. Parameter transfer during module instantiation

    By songlin941111,
    • 4 replies
    • 352 views

  6. Best way to pass parameters trough modules

    By João Paulo,
    • 4 replies
    • 960 views

  7. Creating runtime variable design configuration

    By Andy Tomlin,
    • 3 replies
    • 278 views

  8. ofstream not working inside SC_CTHREAD

    By Nithin,
    • 1 reply
    • 260 views

  9. FIKA

    By mburton,
    • 0 replies
    • 257 views

  10. Requesting Help to Generate `libqt.a` Library Using Qt package available in systemc-2.3.3

    By ARI,
    • 3 replies
    • 312 views

  11. Z80 RTL+SystemC Interactive Co-Simulation

    By goodkook,
    • 1 reply
    • 330 views

  12. How to define `sc_fixed` variables that have word/integer lengths that are based off (but not the same size as!) those of a template parameter

    By monkey_nuts,
    • 4 replies
    • 348 views

  13. 6502 RTL+SystemC Interactive Co-Simulation

    By goodkook,
    • 0 replies
    • 394 views

  14. Carry class in sc_signal and memory allocation

    By David Peng,
    • 3 replies
    • 250 views

  15. how to model timing with interface method?

    By Qian,
    • 2 replies
    • 269 views

  16. What is the benefits or need of exlicitly making an sc_spawn process to be called before the end of elaboration (making it static) simillar benefits of making a SC_METHOD or SC_THREAD invoked from the end of elaboration callback(i.e. to make it dynamic)

    By saswat mund,
    • 3 replies
    • 308 views

  17. how to model registers

    By eritronio,
    • 5 replies
    • 9.1k views

  18. How to force the update of a sc_signal<bool>?

    By Diego,
    • 5 replies
    • 448 views

  19. Creating an array of sc_modules that is synthesizable

    By newtosystemc,   
    • 4 replies
    • 257 views

  20. Example risc_cpu from systemc-2.3.4.zip issues.

    By djmoore,
    • 1 reply
    • 230 views

  21. Prebuilt binary package of SystemC 2.3.3 in C++17 environment

    By Pavankumar,
    • 1 reply
    • 278 views

  22. Making SystemC code synthesizable using Vivado HLS, arrays of ports.

    By newtosystemc,   
    • 1 reply
    • 358 views

  23. SystemC QuickThread

    By Rd7,
    • 3 replies
    • 580 views

  24. SC_ENABLE_SIMULATION_PHASE_CALLBACKS_TRACING doesn't propagate to users of SystemC CMake package

    By Marcus,
    • 2 replies
    • 289 views

  25. fifo problem with my code

    By keroroishappy,
    • 2 replies
    • 281 views
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