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Hello everybody, I was looking for a main topic about synthesizable SystemC here but there is not any one specific about it. I have been learning and working with SystemC to RTL, mostly modelling pure digital systems and trying to do it clock cycle accurate. The last project that I am working on is on model and implement a 32bit processor core. Until now the pure SystemC model is fulfilling the specifications and now I am trying to synthesize it with VIVADO HLS suite. I already checked Accellera Synthesis Subset 1.4.7 and many other kind of manuals or guidelines for that purpose.
i want to consider capability to synthesis of sample systemc code whit agility compiler i faced this error aall (E1064) Ports of type sc_bit are not allowed systemc.h Line:324 Col:13 ag_util.h Line:33 Col:12 header.sc.h Line:1075 Col:2 synthesis.sc.cpp Line:6 Col:5 synthesis.sc.cpp Line:3 Col:6