Is there any way to initialize input port in module?The problem occurs in reset function when i initialize readdata32_16 port.

[fayz]

#include <systemc.h>

SC_MODULE(FETCH) {
    sc_out<sc_int<32>> writedata;
    sc_in < sc_int<32>>readdata32_16;

    sc_in_clk clk;
    sc_int<32>* mem;
    sc_uint<12> pc_value = 0;
    sc_int<32>* ptr; 
    int i = 0;
    sc_in<bool> res;

   

    SC_CTOR(FETCH) {
        int memsize = 4096;
        mem = new sc_int<32>[memsize];  

     /** for (int i = 0; i < memsize; i++) {
            mem[i] = 0;
        }*/

        SC_THREAD(memoryAccessThread);
        sensitive << clk.pos();

        SC_THREAD(checkins);
        sensitive << clk.pos() ;

        SC_THREAD(reset);
        sensitive << clk.pos();
    }

    void memoryAccessThread() {
        while (true) {
            wait();
            if (i >= 0 && i < 4096 && res!=1) { // for Checking bounds of memory before writing
               
                mem[i] = readdata32_16;               
            }
        }
    }

    void checkins() {
        while (true) {
            wait(clk.posedge_event());
            
                if (i >= 0 && i < 4096 && res!=1) { 
                    if (readdata32_16.read().range(31,16)==0){        //for 16 bit instruction
                        writedata.write(mem[i]);
                        pc_value = pc_value + 2;
                        ptr = &mem[i]; 
                        i++;
                        cout << "16 bit running" << endl;
                    }
                    else if (readdata32_16.read() != 0 && res != 1) { //for 32 bit instruction
                        writedata = mem[i];
                        pc_value = pc_value + 4;
                        ptr = &mem[i];                   
                        i++;
                        cout << "32 bit running" << endl;
                    }
                }
            
        }
        
    }

    void reset() {
            while (true) {
                wait(clk.posedge_event());
                if (res == true) {
                    ptr = &mem[0];
                    i = 0;
                    pc_value = 0;
                   readdata32_16 =0 ;
                    writedata = 0;
                    

                }
            }

    }

    
    ~FETCH() {
        delete[] mem; 
    }
};

int sc_main(int argc, char* argv[]) {
    sc_set_time_resolution(1, SC_SEC);
    sc_signal<sc_int<32>> write, read;
   
    sc_signal<bool> reset;
    sc_signal<sc_uint<12>> pcvalue; 
    sc_clock clk("clk", 2, SC_SEC);

    FETCH fetch_module("fetch_module");
    fetch_module.writedata(write);
    fetch_module.readdata32_16(read);
    fetch_module.clk(clk);
    fetch_module.res(reset);

    sc_trace_file* trace_file = sc_create_vcd_trace_file("fetch");
    sc_trace(trace_file, write, "write");
    sc_trace(trace_file, clk, "clk");
    sc_trace(trace_file, read, "read");
    sc_trace(trace_file, reset, "reset");

    
    read = 0x289f45e1;
    sc_start(2, SC_SEC);
    cout << "ptr :" << fetch_module.ptr << endl;

    read = 0x6e3f1290;
    sc_start(2, SC_SEC);
    cout << "ptr :" << fetch_module.ptr << endl;

    read = 0x0000ffff;
    sc_start(2, SC_SEC);
    cout << "ptr :" << fetch_module.ptr << endl;
    reset = true;
    sc_start(2, SC_SEC);
    cout << "ptr :" << fetch_module.ptr << endl;
  /*  read = 0x00e2ffff;
    sc_start(2, SC_SEC);
    cout << "ptr :" << fetch_module.ptr << endl;*/

   

    sc_close_vcd_trace_file(trace_file);

    cout << "pc value :" << fetch_module.pc_value << endl; 

    for (int i = 0; i <= 4095; i++) {
        cout << "memory " << i << ": " << hex << fetch_module.mem[i] << dec << endl;
    }

    return 0;
}

 

 

[AmeyaVS]

Hello @fayz,

Why do you need to initialize the input interface in the same module?
I would probably leave the initial value being defined by the initiator module driving that interface.

Regards,

Ameya Vikram Singh

[fayz]

beacause when i am reseting , I am receiving the previous value,which was read. I want to set it to 0

[David Black]

There is a fundamental SystemC misunderstanding here. Ports do not store data nor do they have any associated "value". A port merely provides access to a channel and specifies which methods are available via the interface. The "value" to be initialized would be in the channel.

sc_in < sc_int<32>>readdata32_16;

The above specifies that readdata32_16 is connected to a sc_signal channel that manages sc_int<32> data. The port uses an sc_signal_in_if interface, which is restricted to using the read() access method. You may not write data via a sc_in port.

Also, you have fundamental misunderstandings about how time moves forward in SystemC. sc_start does not move time. You need to be using sc_core::wait().

Observation: Most of your code in sc_main() should be moved into a thread in a top-level module. Main should only be responsible for instantiating a single top-level module, starting the simulation, and performing clean-up at the end. Stimulus should be placed in a thread. Observation also needs its own SystemC process.

 

[David Black]

One more hint: Try https:://www.EDAplayground.com when learning SystemC. It is easier to share your ideas/problems from there.