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Eyck last won the day on September 1

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  1. SInce the question is already 4 years old I guess there will be now answer. If you need something like the fair mutex you might have a look at the scc::ordered_semaphore which can also be used as a mutex (with a value of one). At https://github.com/Minres/SystemC-Components/blob/main/src/sysc/scc you will find a complete implementation.
  2. Why not use constructor prameters? Another option would be cci_params. Via the broker they can be given a value before they are created. So you can use them in contructor bodies....
  3. You need to implement a method or a thread being sensitive on the clock. Something like: SC_MODULE(test) { sc_core::sc_in<bool> clk_i{"clk_i"}; sc_core::sc_ou<bool> out_o{"out_o"}; SC_CTOR(test) { SC_THREAD(run); } void run(){ while(true) { wait(clk_i.posedge_event()); out_o.write(!out_o.read()); } } };
  4. You can find a complete implementation of a memory here: https://github.com/Minres/SystemC-Components/blob/main/src/components/scc/memory.h or here: https://git.minres.com/SystemC/PySysC-SC/src/branch/master/components/target.cpp The latter has also a toplevel: https://git.minres.com/SystemC/PySysC-SC/src/branch/master/top/ BR
  5. Well, t_socket[i] is a pointer. So with o_tb[i]->bind(m_abc->t_socket[i]); you are calling bind with a pointer. There is no such function defined. I would suggest to refrain from using raw pointers and C-style arrays as they harm more than helping you. I coded up an example at https://www.edaplayground.com/x/MTTy If you are going to build up a really big design then you should use a std::unique_ptr with std::make_unique in your sc_main function only. This way all design elements will be instantiated using a single new call...
  6. the simple_target_socket_tagged does tell the callback which socket called the callback not which initiator. So you need to have a target socket for each of your peripherals. A use example of tagged sockets can be found at https://www.doulos.com/httpswwwdouloscomknowhow/systemc/tlm-20/tutorial-3-routing-methods-through-interconnect-components/ where simple_initiator_socket_:tagged is used for the router. The use of simple_target_socket_tagged is similar.
  7. TGC is 'The Good Core' family of RISC-V cores of MINRES Technolgis GmbH. The VP-Vibes organization at Github is for any project related to Virtual Prototypes. So the SystemC-Components library comes with SystemC utilities, components like register and generic bus targets as well as on-chip interconnect protocol definitions. The VPV-Peripherals provides peripherals which can be used in building VPs while the TGC-VP assembles all these components into a VP. Parts of the VP, in detail the ISS and its infrastructure, is being used as reference model to verify the RTL implementation(s). For this we use an insturction stream generator and a response checker (see also here).
  8. tri-state logic is not synthesizable. But if you use a 2-bit vector where one bit shows activity and one bit the value this can be synthesized... But it doubles the number af wires and depending on the gate logic the size of the logic. This may be wroked around by designing a custom cell for the standard cell library. After it is characterized the cell might be used by the synthesizer.
  9. Yes, you are writing 2 elements into the fifo in the same evaluation phase. This results in a single notification of the data wrtitten event. The returned value tells you if the write was succesfull or not. How to react on that depends on your model. At least you have to try it again at a later time (e.g. when the fifo has room for the new element). The delta cycle does not change. But I guess you mean when does the function return. For this you can consult the LRM. But in short: nb_write returns immediately, it is non-blockin (or nb). Therefore you can use it in an SC_METHOD. write is blocking which means internally wait is called and it returns once the element has been placed in the fifo. Therefor write can only be used in SC_THREAD since the call to wait() is not allowed in SC_METHOD.
  10. There are quite few more RISC-V ISS/VPs, all based on SystemC. E.g.: ETISS of TU München (https://github.com/VP-Vibes/etiss) TGC-VP of MINRES (https://github.com/VP-Vibes/TGC-VP)
  11. There are no SystemC specific profiling tools freely available. So either you use tools of well-know EDA vendors or used gprof, valgrind, ptrace, or alike to profile your simulation. Unfortunately they are not aware of sc_threads (or coroutines) so some creativity is needed to interpret the results. I would also put some emphasis on memory allocation and managment. If the footprint gets larger caches need to be more often flushed and this cost quite some time.
  12. The simplest solution would be to pass a pointer (or reference) to OS_Task or the TCB with task_create() and task_end(). A forward declaration alogn with the OS_API class should be sufficient. I don't know your requirements but it seems to me that your use of sc_module is sub-optimal for the purpose of modeling OS tasks. The reason is simple: you cannot create or delete sc_module after the elaboration phase. And OS tasks tend to be dynamic... So sc_object and sc_spawn might be a better solution. I assume that task_create() and task_end() always surround the behavior of a task. So why not move them into the OS_Task itself? If you pass then the TCB as pointer or by reference you could encapsulate the entire stuff of task handling in the OS_task class...
  13. I took your eample and pasted it at https://www.edaplayground.com/x/EtqQ From there is works without any hassle. You seem to have anything different in your code base than posted here.
  14. C++17 supports the inline static syntax (see https://en.cppreference.com/w/cpp/language/static). So you need to have a C++17 capable compiler and specify the language level accordingly. In C++14 this is not supported....
  15. tlm_fifo provides a blocking read called get() as well as an event to use: ok_to_get(). To block the writer you can use ok_to_put() which is triggered when the fifo is read.
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