newtosystemc Posted May 28, 2023 Report Share Posted May 28, 2023 Hello everyone, i am very new to both systemc and HLS. I have systemc code that I am trying to synthesize using Vivado HLS 2019.2 (since it still supports Systemc). The systemc code works fine but was not originally written for Synthesis and I am trying to make it synthesizable. I have a problem since the source code has arrays of ports for example: sc_in<sc_int<8>> input [10]; sc_out<sc_int<8>> output[10]; that are connected to arrays of signals, example: sc_signal<sc_int<8>> sig[10]; What is the best way to making the code synthesizable? I tried pragmas but the arrays are defined in the SC_Module in the header files and not inside functions, I believe this is causing the following error: ERROR: [HLS 200-70] '#pragma HLS ARRAY_PARTITION variable=input type=complete dim=0' is not a valid pragma I also tested using sc_in<sc_lv<80>> input , however I am not sure of connecting the port to a signal array since using input.read().range(0,8)(sig[0]); is causing errors and also i am not sure how to connect sc_out with another sc_out when using sc_lv. Thanks in advance for your help!! Quote Link to comment Share on other sites More sharing options...
newtosystemc Posted May 29, 2023 Author Report Share Posted May 29, 2023 EDIT: the Pragma was indeed an invalid Pragma. I edited it to #pragma HLS ARRAY_PARTITION variable=input complete dim=0 Which results in the ERROR: Pragmas need to be inside functions. I created a function that I call in the constructor of the Module which defines the pragmas. Now I get the error Unsupport array declarator of port. Which I get with no Pragmas as well. I suppose it indicates that I am using arrays of ports which is not synthesizable. Meaning the Pragmas are not working in this case. Does anyone have any suggestions? Quote Link to comment Share on other sites More sharing options...
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