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Nithin

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  1. Hi, Thank you David and "basarts" One follow up question on this. I found that it is possible to use SYSCAN to instantiate C-models in RTL testbench and do VCS simulation. Unfortunately SYSCAN is having some issues with latest version of VCS. I am wondering if there is some way to get rid of SYSCAN and use some other method to run VCS simulation in RTL testbench with C-model instantiation. Thanks in advance. Regards, Nithin
  2. Hi, I am trying to dump internal signals of an SC_MODULE's processes (SC_THREAD process) in a VCD. SC_MODULE has multiple processes and I need to dump signals from each of those processes in the same VCD. Currently, I am trying with one SC_THREAD process and I see this error when I add sc_trace inside the while loop: Error: (E720) sc_trace_file already initialized: sc_trace() failed: No traces can be added to 'traces.vcd' once trace recording has started. To add tracing of 'A_val', create a new trace file. In file: ../../../src/sysc/tracing/sc_trace_file_base.cpp:239 Here is my code: SC_MODULE (SUM) { sc_in<sc_int<10>> A; sc_in<sc_int<10>> B; sc_out<sc_int<10>> S; sc_trace_file* Tf; void do_sum(); SC_CTOR (SUM) { Tf = sc_create_vcd_trace_file("traces"); SC_THREAD(do_sum); sensitive << A << B; } ~SUM() { sc_close_vcd_trace_file(Tf); } }; void SUM::do_sum() { int A_val, B_val, S_val; while(true) { wait(); A_val = A.read(); B_val = B.read(); S.write(A.read()+B.read()); S_val = A_val + B_val; sc_trace(Tf, A_val, "A_val"); sc_trace(Tf, B_val, "B_val"); sc_trace(Tf, S_val, "S_val"); } } Can someone please help me with this? Thanks in advance. Regards, Nithin
  3. Hi, Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets? Thanks in advance. Regards, Nithin
  4. Hi, I am a beginner in SystemC. I am trying to create a small testcase to add two numbers. The inputs are defined as sc_fifo_in, and these are added to the sensitivity list for SC_THREAD. SC_THREAD process is somehow not responding to the sensitivity list Is there any way I can define the two sc_fifo_in signals (A_val_in and B_val_in) the sensitivity list of do_sum process? class sum : public sc_core::sc_module { public: SC_HAS_PROCESS(sum); sc_core::sc_fifo_in<sc_int<10>> A_val_in; sc_core::sc_fifo_in<sc_int<10>> B_val_in; sc_core::sc_fifo_out<sc_int<10>> S_val_out; sc_event sum_finished; sc_event input_event; void do_sum(); sum (const char* name) : sc_core::sc_module(name) { std::cout << "DBG: Inside constructor\n"; SC_THREAD(do_sum); sensitive << A_val_in << B_val_in; } }; void sum::do_sum() { while(true) { wait(); std::cout << "DBG: Inside do_sum\n"; unsigned int Sint = A_val_in.read() + B_val_in.read(); S_val_out.write(Sint); std::cout << "DBG: Inside do_sum: Sum = " << Sint << std::endl; sum_finished.notify(SC_ZERO_TIME); } } Please let me know if you need any more information. Thanks in advance, Nithin
  5. Hi, Is it possible to trigger an SC_THREAD based on bool value rather than the edge? For eg: SC_THREAD(a_func) sensitive <<A a_func should be called when A = 1 (not when A transitions from 0 to 1). Is this possible? Thanks, Nithin
  6. Hi, I am trying to create a simple SystemC code to add two numbers. Here is my code: class sum : public sc_core::sc_module { public: SC_HAS_PROCESS(sum); sc_core::sc_in<sc_int<10>> A_val_in; sc_core::sc_in<sc_int<10>> B_val_in; sc_core::sc_inout<sc_int<10>> S_val_out; void do_sum(); sum (const char* name) : sc_core::sc_module(name) { SC_THREAD(do_sum); sensitive << A_val_in << B_val_in; } }; void sum::do_sum() { while(true) { wait(); std::cout << "DBG: Inside do_sum\n"; sc_int<10> A = A_val_in.read(); sc_int<10> B = B_val_in.read(); sc_int<10> S = A + B; S_val_out.write(S); std::cout << "DBG: Inside do_sum: A_val_in = " << A_val_in << ", B_val_in = " << B_val_in << std::endl; std::cout << "DBG: Inside do_sum: A = " << A << ", B = " << B << std::endl; std::cout << "DBG: Inside do_sum: S = " << S <<std::endl; std::cout << "DBG: Inside do_sum: S_val_out = " <<S_val_out<< std::endl; } } I feel there is some problem with S_val_out.write(S) command as highlighted below. Here is the print messages. S_val_out is always 0. I tried changing the definition of S_val_out to sc_out. But it is not helping. DBG: Inside do_sum DBG: Inside do_sum: A_val_in = 5, B_val_in = 10 DBG: Inside do_sum: A = 5, B = 10 DBG: Inside do_sum: S = 15 DBG: Inside do_sum: S_val_out = 0 Can someone please help me to understand what the problem is? Thanks in advance. Regards, Nithin
  7. Hi, I am new to SystemC. Can someone please explain the difference between sc_fifo and sc_fifo_in? Thanks in advance. Regards, Nithin
  8. Hi, I am getting similar error. But I don't understand how to bind the ports for this. Can someone please help? Here is the error: SystemC 2.3.3-Accellera --- Aug 13 2020 01:41:43 Copyright (c) 1996-2018 by all Contributors, ALL RIGHTS RESERVED Error: (E109) complete binding failed: port not bound: port 'top.port_2' (sc_inout_rv) In file: ../../../src/sysc/communication/sc_port.cpp:235 Here is the SystemC code: #include <systemc.h> SC_MODULE(module_A) { sc_in_rv<1> in; sc_out_rv<1> out; sc_inout_rv<4> inout; void body () { out.write(0); if (in.read() == 1) { out.write(1); inout.write(rand()); } else { out.write('z'); inout.write("zzzz"); } } SC_CTOR(module_A) { SC_METHOD(body); sensitive << in; } }; module_A *top = NULL; int sc_main (int argc, char* argv[]) { top = new module_A("top"); sc_start(); return(0); }
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