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  1. Hi, Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets? Thanks in advance. Regards, Nithin
  2. Hi, I am a beginner in SystemC. I am trying to create a small testcase to add two numbers. The inputs are defined as sc_fifo_in, and these are added to the sensitivity list for SC_THREAD. SC_THREAD process is somehow not responding to the sensitivity list Is there any way I can define the two sc_fifo_in signals (A_val_in and B_val_in) the sensitivity list of do_sum process? class sum : public sc_core::sc_module { public: SC_HAS_PROCESS(sum); sc_core::sc_fifo_in<sc_int<10>> A_val_in; sc_core::sc_fifo_in<sc_int<10>> B_val
  3. Hi, Is it possible to trigger an SC_THREAD based on bool value rather than the edge? For eg: SC_THREAD(a_func) sensitive <<A a_func should be called when A = 1 (not when A transitions from 0 to 1). Is this possible? Thanks, Nithin
  4. Hi, I am trying to create a simple SystemC code to add two numbers. Here is my code: class sum : public sc_core::sc_module { public: SC_HAS_PROCESS(sum); sc_core::sc_in<sc_int<10>> A_val_in; sc_core::sc_in<sc_int<10>> B_val_in; sc_core::sc_inout<sc_int<10>> S_val_out; void do_sum(); sum (const char* name) : sc_core::sc_module(name) { SC_THREAD(do_sum); sensitive << A_val_in << B_val_in; } }; void sum::do_sum() { while(true) {
  5. Hi, I am new to SystemC. Can someone please explain the difference between sc_fifo and sc_fifo_in? Thanks in advance. Regards, Nithin
  6. Hi, I am getting similar error. But I don't understand how to bind the ports for this. Can someone please help? Here is the error: SystemC 2.3.3-Accellera --- Aug 13 2020 01:41:43 Copyright (c) 1996-2018 by all Contributors, ALL RIGHTS RESERVED Error: (E109) complete binding failed: port not bound: port 'top.port_2' (sc_inout_rv) In file: ../../../src/sysc/communication/sc_port.cpp:235 Here is the SystemC code: #include <systemc.h> SC_MODULE(module_A) { sc_in_rv<1> in; sc_out_rv<1> out; sc_inout
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