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SystemC Language

1,297 topics in this forum

  1. How to display binding hierarchy?

    By Yash,   
    • 2 replies
    • 596 views

  2. Phasing tests in a testbench: An elegant way of doing this?

    By Rayane Chatrieux,   
    • 3 replies
    • 419 views

  3. Segmentation fault (core dumped)

    By acc_sysC,
    • 4 replies
    • 942 views

  4. How to schedule interrupt to trigger for next time?

    By Minu,   
    • 2 replies
    • 553 views

  5. Type casting and concatenation

    By amitk3553,
    • 8 replies
    • 8.5k views

  6. MSAN issue with DECLARE_EXTENDED_PHASE macro

    By tmp_sc,   
    • 0 replies
    • 372 views

  7. Dynamic Module in SystemC

    By Mohammad,
    • 1 reply
    • 539 views

  8. Synthesize SystemC code in Vitis HLS 2022.1

    By Rd7,
    • 4 replies
    • 1.6k views

  9. Valgrind issue with sc_event

    By DS1701,
    • 3 replies
    • 1.2k views

  10. Is Y[(G%M)*(1<<N)*(G/M)] = X.read()[G] allowed?

    By acc_sysC,
    • 2 replies
    • 357 views

  11. How to do this port declaration in systemC? Verilog declaration: input [$clog2(N)-1] X;

    By acc_sysC,
    • 3 replies
    • 659 views

  12. Any good Example of TLM generic payload extension .. with Initialtor and Target socckets

    By chaitusvk,
    • 2 replies
    • 735 views

  13. Can pow() be directly used as size of port during port declaration?

    By acc_sysC,
    • 2 replies
    • 391 views

  14. was not declared in this scope error

    By acc_sysC,
    • 5 replies
    • 875 views

  15. Timer with interrupts using Loosely Timed Implementation

    By Minu,   
    • 1 reply
    • 469 views

  16. How to Print DEBUG_MSG in "sysc/kernel/sc_runnable_int.h"

    By chaitusvk,   
    • 1 reply
    • 445 views

  17. How to implement adding function using next_trigger in SC_METHOD?

    By Minu,
    • 3 replies
    • 625 views

  18. In Which function of Systemc Code thread Switch happen ?

    By chaitusvk,   
    • 2 replies
    • 417 views

  19. gdb for systemc model

    By LaoShaw,
    • 1 reply
    • 974 views

  20. Should SystemC model be exactly same as the RTL in terms of the architecture of each module?

    By acc_sysC,
    • 2 replies
    • 416 views

  21. Is it possible to perform AND operation on two ports and connect them while instatiating?

    By acc_sysC,
    • 2 replies
    • 430 views

  22. Error: (E529) insert module failed: simulation running

    By acc_sysC,
    • 7 replies
    • 860 views

  23. What happens in SC_HAS_PROCESS()?

    By tanlt,
    • 2 replies
    • 2.4k views

  24. Assign sc_lv to sc_vector<sc_signal<sc_logic>>>

    By Stefan,
    • 0 replies
    • 418 views

  25. Compiling SystemC on ARM

    By Matthias Jung,   
    • 3 replies
    • 2.5k views
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