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Showing results for tags 'hls'.
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juan posted a topic in SystemC LanguageHello everybody, I was looking for a main topic about synthesizable SystemC here but there is not any one specific about it. I have been learning and working with SystemC to RTL, mostly modelling pure digital systems and trying to do it clock cycle accurate. The last project that I am working on is on model and implement a 32bit processor core. Until now the pure SystemC model is fulfilling the specifications and now I am trying to synthesize it with VIVADO HLS suite. I already checked Accellera Synthesis Subset 1.4.7 and many other kind of manuals or guidelines for that purpose. I am using SC_SIGNAL as channel between methods inside the same module I have the sc_signal defined as: sc_core::sc_signal<sc_dt::sc_bv<32> > register and it is added to the sensitivity list in the following way: SC_METHOD(prc_assign_rf_reg); sensitive << register; sensitive << register; .... down to sensitive << register; My question is somebody knows or have in mind some other way to implement the sensitivity list of this multidimensional signal array or could advice me another way to implemented, in order to firstly avoid to instance every array row position in the sensitivity list and secondly to implement this type of vector memory in another way. Thanks for your attention and support. Juan
Synthetizable FFT function in SystemC
Teddy Minz posted a topic in SystemC LanguageHi everyone, As part of my job I try to implement a FFT function in my ZedBoard. I found some example including one in the SystemC folder unfortunately not synthesizable. Furthermore, I use a free version of Vivado HLS and this tool is very restrictive (few things are synthesizable). So, I will going to have to code my own version of this function (8k/16k/32k FFT). For doing this, I started by cut the FFT's mathematical formula and try to code a exponential function. I realized I can't use the "math.h" library and then I have to code all with only logic gates. At this level, I prefer to code directly in VHDL. Does anyone have a experience with this synthesis tool and can give me a simpler way to achieve my goal ? Maybe I see the problem of the wrong angle. Best regards
2 Complement with sc_fixed type and HLS
campo85 posted a topic in SystemC LanguageHi all, I'm quite new to all the SystemC world. As far as I got the sc_fixed type should be synthesizable. My problem at the moment is that I have a number, and I need the negative version of that number. The easiest way to do it is to multiply for -1. The problem is the HLS. I actually don't know how this it will be handled by the tool. I would like to avoid to instantiate a multiplier just to do a simple 2 complement operation ( flip the bits and adding 1 to the LSB ). If I can't trust the HLS tools I guess the safest way would be to do the 2 complement by myself, but even there I have some concern : sc_fixed <8,3,SC_RND,SC_SAT> foo, foo_neg; foo_neg = ~foo + 2^(8-3) ( PSEUDOCODE : I still need to figure out ) I don't really like to add 2^-5, it isn't clean. Even here probably it's easier to convert in int and add 1, but still it's quite messy in my opinion. Does anyone know if the tools are smart enough to handle correctly a multiplication between sc_fixed type and -1 and to implement correctly the 2 complement operation? If not how should I need to proceed ?