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Showing results for tags 'hls'.
Hello everybody, I was looking for a main topic about synthesizable SystemC here but there is not any one specific about it. I have been learning and working with SystemC to RTL, mostly modelling pure digital systems and trying to do it clock cycle accurate. The last project that I am working on is on model and implement a 32bit processor core. Until now the pure SystemC model is fulfilling the specifications and now I am trying to synthesize it with VIVADO HLS suite. I already checked Accellera Synthesis Subset 1.4.7 and many other kind of manuals or guidelines for that purpose.
Hi everyone, As part of my job I try to implement a FFT function in my ZedBoard. I found some example including one in the SystemC folder unfortunately not synthesizable. Furthermore, I use a free version of Vivado HLS and this tool is very restrictive (few things are synthesizable). So, I will going to have to code my own version of this function (8k/16k/32k FFT). For doing this, I started by cut the FFT's mathematical formula and try to code a exponential function. I realized I can't use the "math.h" library and then I have to code all with only logic gates. At this level, I prefer to co
Hi all, I'm quite new to all the SystemC world. As far as I got the sc_fixed type should be synthesizable. My problem at the moment is that I have a number, and I need the negative version of that number. The easiest way to do it is to multiply for -1. The problem is the HLS. I actually don't know how this it will be handled by the tool. I would like to avoid to instantiate a multiplier just to do a simple 2 complement operation ( flip the bits and adding 1 to the LSB ). If I can't trust the HLS tools I guess the safest way would be to do the 2 complement by myself, but even there I