Questions about SystemC simulation time

[YYF]

Dear experts, I am new to SystemC and interested in discussing SystemC simulation time.

I'm having a problem with systemc simulation time, and I've learned that systemc can't do system-level parallelism, just simulates a hardware parallelism behavior.
However, at the moment I have a larger project, such as:

I have a top-level module SC_MODULE (A), and two submodules SC_MODULE (B) and SC_MODULE (C), A and B, A and C, B and C all communicate via FIFO.
1: As long as the FIFO is not satisfied, will each module not affect each other's independent operation in CPU simulation?

In addition, there are multiple threads SC_CTHREAD  (a_1) and SC_CTHREAD (a_2) inside SC_MODULE (A).
There are multiple threads SC_CTHREAD (b_1) and SC_CTHREAD (b_2) in SC_MODULE(B).
There are multiple threads SC_CTHREAD (c_1) and SC_CTHREAD (c_2) in SC_MODULE(C).
I did some tests, A alone runs it takes 1200s (remove the FIFO for B and C), B takes 300s to run alone (read .txt file as input), C alone takes 100s (read .txt file as input).
So A+B+C run together (A sends data to B/C through FIFO), ideally in parallel, the maximum time should be 1200s? But according to my current understanding of SystemC, maybe the time should be 1200+300+100 = 1600s?
But actually I did the simulation time to reach about 4000s, what is the reason? Please help with the experts, or help me explain the SystemC parallel time problem in depth.

Any help is appreciated.

yyf

[David Black]

First, the statement "systemc can't do system-level parallelism" is misleading and depends significantly on what you are trying to do. SystemC uses an event-driven simulation model in the same vein as VHDL and SystemVerilog. It can simulate parallism (concurrency) for both hardware and software, when correctly used.

Second, your description of what you are doing is not clear. Please provide:

1. a diagram illustrating module boundaries, processes, and FIFOs
2. provide your code (ideally on EDAplayground).

 

[YYF]

7 minutes ago, David Black said:

First, the statement "systemc can't do system-level parallelism" is misleading and depends significantly on what you are trying to do. SystemC uses an event-driven simulation model in the same vein as VHDL and SystemVerilog. It can simulate parallism (concurrency) for both hardware and software, when correctly used.

Second, your description of what you are doing is not clear. Please provide:

1. a diagram illustrating module boundaries, processes, and FIFOs
2. provide your code (ideally on EDAplayground).

 

Thanks for your reply.

Here is the simple code I provided

//"top_module.h"
sc_uint<32> transmit_top2sub_msg;

SC_MODULE(top_module){
  sc_in_clk        clk;
  sc_in  <bool>     rst_n;
  sc_fifo_out <sc_biguint<32> >     top2sub;
 
  bool top_compute = false;
  bool top2sub = false;

  void top_module_compute(); // The calculation logic of the top layer
  void transmit_top2sub(); // The result calculated by the top layer is passed to the sub module via FIFO
  
  SC_CTOR(top_module)
   {
     SC_CTHREAD(top_module_compute, clk.pos());
     SC_CTHREAD(transmit_top2sub, clk.pos());
    }
}

//"top_module.cpp"
#include "top_module.h"

void top_module::top_module_compute(){
  while(true){
    while(top_compute) wait();
    
    transmit_top2sub_msg = 8;
    top2sub = true;
    top_compute = true;
   }
}

void top_module::transmit_top2sub(){
  while(true){
    while(!top2sub) wait();

    while(top2sub.num_free() == 0) wait();
    top2sub.write(transmit_top2sub_0_msg);
    wait();
    
    top_compute = false;
    }
}

//"sub_module.h"
sc_biguint<32> sub_msg;
SC_MODULE(sub_module){
  sc_in_clk        clk;
  sc_in  <bool>     rst_n;
  sc_export<sc_fifo_out_if<sc_biguint<32>>>  top2sub;
  sc_fifo<sc_biguint<32>>  top2sub_fifo;

  bool msg_ready = false;
  
  void parse_pkt(); //Used to receive data sent by the top layer via FIFO
  void sub_compute(); //The sub module calculates logic from the received data
  
  SC_CTOR(sub_module)
   {
     SC_CTHREAD(parse_pkt, clk.pos());
     SC_CTHREAD(sub_compute, clk.pos());
    }
}

//"sub_module.cpp"
#include "sub_module.h"
void sub_module::parse_pkt(){
  while(true){
    if (top2sub_fifo.num_available() > 0){
      sub_msg = top2sub_fifo.read();
      msg_ready = true;
    }else{
      wait();
    }
  }
}

void sub_module::sub_compute(){
  while(true){
    while(!msg_ready) wait();
    // use sub_msg compute
    msg_ready = false; 
  }
}

Here I listed a transport layer and a receiving layer, which sc_main not shown. This is my main way of coding at the moment, and it is written in a hurry, just to make a short explanation, if there are grammatical errors, hopefully understand.

So my problem is that if top is simulated independently, its total run time may be over in 1000s (stop conditions are not shown in the example code above). Sub standalone simulation can be over in 500s.

However, in fact, the top and sub run together, the simulation time will probably reach 4000s, if I say that I am not parallel, I understand that the simulation time is at most 1500-2000s, so I am confused why the simulation time is so long.

Thank you for your answer

[Andy Goodrich]

It would help to know the stop conditions, as they affect the simulation time. When you say the simulation runs for a number of seconds, are you talking about simulation clock time, or wall clock time?

[David Black]

How about transferring your code onto EDAplayground.com? You can then add statements to show time there. Then share the link.