Z80 RTL+SystemC Interactive Co-Simulation

[goodkook]

Z80 RTL+SystemC Interactive Co-Simulation

SystemC is C++. That means "Can Do Any Thing." I made interactive co-simulation environment. I made this Co-Sim environment as an example to teach college students "What can do with SystemC. It is C++, Not just another HDL." at Kyunghee University, Korea.

1. RTL Simulator: QuestaSim Starter FPGA Edition (intel)
2. C++ Compiler: VisualStudio 2022 Community Edition
3. Z80 RTL: https://github.com/Time0o/z80-verilog
4. Monitor: https://sites.google.com/site/ericmklaus/projects-1/z80minisystem
5. SystemC/C++: I made followings,
    - Memory model
    - Peripheral model
    - Windows' Pipe IPC(inter-process communication) is used for interaction between RTL simulator and Terminal.

See following moving GIF:

 

Kook (goodkook@gmail.com)

 

[Eyck]

Did you try using Verilator with its SystemC wrapper? Not everyone has access to Quartus or wants to install it. And it removes the burden to have a co-simulation...