Chinmayks17 Posted May 26, 2022 Report Share Posted May 26, 2022 Hi, I have a memory class extended from uvm_mem like below, class mem_top_my_mem extends uvm_mem; function new(string name = "my_mem"); super.new(name, `UVM_REG_ADDR_WIDTH'h30000000, 32, "RW", build_coverage(UVM_NO_COVERAGE)); endfunction : new virtual function void build(); endfunction : build `uvm_object_utils(mem_top_my_mem) endclass : mem_top_my_mem I have a top_mod class extended from uvm_Reg_block in which I want to add this memory with base address as 'h1000_0000. I am doing it in build phase as below, default_map.add_mem(this.my_mem, 'h10000000, "RW"); But the base address being returned from the RAL is zero. Anything I'm missing here? If I declare another class 'mod_top_my_mem' extended from uvm_reg_block and do add_mem there and add instance of this using 'add_submap' in the top_mod class (base address specified in add_submap and not in add_mem), it works fine. Is this some issue with the package or something I have missed? Please help me figure out the reason for this. Found some similar discussion from a decade back here but not sure if it's relevant now: Quote Link to comment Share on other sites More sharing options...
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