referencing an array of uvm_analysis_imp in a scoreboard

[makers78]

I have been working with SV UVM for about 6 months now, over that time I've learned a combination of 1.0 and 1.1 so things are getting a bit confused. I am building a new scoreboard component working with new interface UVCs I created. I have a DUT with multiple identical interfaces which I want to feed into my scoreboard. I am trying to figure out how these uvm_analysis_imp classes are built and what I can access, in particular how I can access the index of a given handle. My thought is something like this:

class packet_scoreboard #(parameter NUM_IF=2) extends uvm_scoreboard;

`uvm_analysis_imp_decl(_pkt_in)

uvm_analysis_imp_pkt_in #( packet_in, packet_scoreboard ) pkt_in[NUM_IF-1:0];

...

function new ( string name = "packet_scoreboard" );

super.new(name);

for ( int i = 0; i < NUM_IF; i++ )

pkt_in = new( $sformatf("pkt_in[%0d]", i), this);

endfunction

virtual function void write_pkt_in( packet_in pkt );

...

uvm_report_info( get_type_name(), $sformatf("Received packet on interface %0d", ???), UVM_DEBUG );

...

endfunction

endclass

Thanks,

Matt

[uwes]

what about the following path: (better then the _decl macros)

-----

class listener #(type E,T) extends uvm_subscriber #(T);

local int idx;

function new(string name, E parent,int idx);

super.new(name,parent);

this.idx=idx;

endfunction // new

function void write(input T t);

E p;

$cast(p,parent);

p.writeit(t,idx)

endfunction

endclass

then make your array of subscribers and new it with the idx.

/uwe

[makers78]

That looks interesting...

The _decl macros are declared inside the component they are used with, I am not sure exactly what they do. I assume this class declaration is made outside of the scoreboard component? Then I create a function in my scoreboard called writeit() which handles what would be in the write function created by the _decl macro?

Thanks!

Matt

[makers78]

I created the class, although I had to use "uvm_component parent" in the new function instead of "E parent". I am running into a problem with the connection in my testbench... the interface UVC is called blk_cqm_master, the module scoreboard is intc_pe_cqm_m_monitor and it has a parameter with a default value set to 8. I get the following error message:

ncelab: *E,TYCMPAT (./tb/cqm_base_tb.sv,172|78): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_port_base#(.IF(class uvm_tlm_if_base#(.T1(class intc_pe_blk_cqm_i_transfer),.T2(class intc_pe_blk_cqm_i_transfer))))' but found 'class intc_pe_cqm_m_blk_cqm_subscriber#(.T(class intc_pe_blk_cqm_i_transfer),.E(class intc_pe_cqm_m_monitor#(.NUM_BLK_CQM_IF(32'h00000008))))' instead).

Do I need to do something to make a uvm_subscriber class compatible with a uvm_port_base pointer?

[makers78]

I figured out the issue... my previous implementation was creating uvm_analysis_imp handles which I was connecting with the uvm_analysis_port.connect() function. I replaced those uvm_analysis_imp handles with uvm_subscriber components, each of which contain an analysis_export. I just added ".analysis_export" to the connect function and it works!

Thanks!

[fbochud]

Thanks, this worked for me as well.

I didn't have to change to "uvm_component parent" in the new function, but had to write:

$cast(p,m_parent);

in the write function. Looks like the member has changed name (I am using UVM 1.1)

[Stars]

On 5/9/2012 at 8:51 PM, makers78 said:

I created the class, although I had to use "uvm_component parent" in the new function instead of "E parent". I am running into a problem with the connection in my testbench... the interface UVC is called blk_cqm_master, the module scoreboard is intc_pe_cqm_m_monitor and it has a parameter with a default value set to 8. I get the following error message:

ncelab: *E,TYCMPAT (./tb/cqm_base_tb.sv,172|78): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_port_base#(.IF(class uvm_tlm_if_base#(.T1(class intc_pe_blk_cqm_i_transfer),.T2(class intc_pe_blk_cqm_i_transfer))))' but found 'class intc_pe_cqm_m_blk_cqm_subscriber#(.T(class intc_pe_blk_cqm_i_transfer),.E(class intc_pe_cqm_m_monitor#(.NUM_BLK_CQM_IF(32'h00000008))))' instead).

Do I need to do something to make a uvm_subscriber class compatible with a uvm_port_base pointer?

Hi. Can anyone post an example of the scoreboard class implementation when using this method. I'm confused at the part where we'd create an object of the parameterized subscriber class.

[Chrich]

On 5/9/2012 at 3:38 AM, makers78 said:

I have been working with SV UVM for about 6 months now, over that time I've learned a combination of 1.0 and 1.1 so things are getting a bit confused. I am building a new scoreboard component working with new interface UVCs I created. I have a DUT with multiple identical interfaces which I want to feed into my scoreboard. I am trying to figure out how these uvm_analysis_imp classes are built and what I can access, in particular how I can access the index of a given handle. My thought is something like this:

class packet_scoreboard #(parameter NUM_IF=2) extends uvm_scoreboard;

`uvm_analysis_imp_decl(_pkt_in)

uvm_analysis_imp_pkt_in #( packet_in, packet_scoreboard ) pkt_in[NUM_IF-1:0];

...

function new ( string name = "packet_scoreboard" );

super.new(name);

for ( int i = 0; i < NUM_IF; i++ )

pkt_in = new( $sformatf("pkt_in[%0d]", i), this);

endfunction

virtual function void write_pkt_in( packet_in pkt );

...

uvm_report_info( get_type_name(), $sformatf("Received packet on interface %0d", ???), UVM_DEBUG );

...

endfunction

endclass

Thanks,

Matt

Can you please share your code or explain here how did you fix that issue ?  
Even i need to have the same support i.e need multiple analysis imports inside the Scoreboard based on nur_of_interfaces {exactly like this :uvm_analysis_imp_pkt_in #( packet_in, packet_scoreboard ) pkt_in[NUM_IF-1:0]; }. My Scoreboard code also the same as above you mentioned but when i use like this, i am ending up with the below compile error while creating the ports inside the  build_phase as below:  

inside build_phase();
for( int i=0;i<NUM_IP_INSTANCES;i++) begin
      tx_xact_observed_port =new($sformatf("tx_xact_observed_port[%0d]",i),this);
      rx_xact_observed_port =new($sformatf("rx_xact_observed_port[%0d]",i),this);
 end

Error :

** Error: ** while parsing file included at testbench.sv(6)
** at test_can.sv(56): 'new' expression can only be assigned to a class or cover group variable.
** while parsing file included at testbench.sv(6)

Thank you,

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