Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

[Abdul Razak H S]

design.sv

module half_adder(a,b,sum,carry);
  input a,b;
  output sum,carry;
  assign sum=a^b;
  assign carry=a&b;
endmodule

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top.sv

import uvm_pkg::*;
`include "uvm_macros.svh";
`include "transaction.sv"
`include "interface.sv"
`include "driver.sv"

module top();
  
  if1 if_h();
  transaction xtn;
//   driver d;
  
  half_adder dut(.a(if_h.a),.b(if_h.b),.sum(if_h.sum),.carry(if_h.carry));

  initial begin
    uvm_config_db #(virtual if1)::set(null,"*","vif",if_h);
  end
    
  initial
     begin
       driver d;
       d = new();
      // $display("hello",d.a);
       d.drive();
     end 
endmodule

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interface.sv

interface if1();
 logic a;
 logic b;
 logic sum;
 logic carry;
 
//   modport port(input a,b,output sum,carry);
endinterface

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transaction.sv

class transaction extends uvm_sequence_item;
  //$display("CODE");
  rand bit a;
  rand bit b;
  bit sum;
  bit carry;
  
  `uvm_object_utils_begin(transaction)
      `uvm_field_int(a,UVM_ALL_ON)
      `uvm_field_int(b,UVM_ALL_ON)
      `uvm_field_int(sum,UVM_ALL_ON)
      `uvm_field_int(carry,UVM_ALL_ON)
  `uvm_object_utils_end
 // $display("WORKING");
  
  
  
  function new(string name = "transaction");
    super.new(name);
  endfunction
  
  endclass

-----------------------------------------------------------------------------------------------------------------------------

driver.sv

class driver extends uvm_driver;
  
    `uvm_component_utils(driver)
  
  virtual if1 vif;
 
  transaction xtn;
  
  function new(string name="driver",uvm_component parent=null);
    super.new(name,parent);
    xtn=new();
  endfunction
  
  function void build_phase(uvm_phase phase); 
    if(!uvm_config_db #(virtual if1)::get(this,"","vif",vif))
      `uvm_fatal("no connection","ERROR"); 
        super.build_phase(phase);

  endfunction

  task drive();
    //xtn=new;
    //xtn=transaction::type_id::create("xtn");
    vif.a=0;
    vif.b=0;
    repeat(10) begin
    xtn.randomize();
    vif.a=xtn.a;
    vif.b=xtn.b;
    #5;
      $display("a=%d,b=%d,sum=%d,carry=%d",xtn.a,xtn.b,vif.sum,vif.carry);
    end
    
    $display("yeeeeee!!!!working");
  endtask
  
endclass

I have used only driver, to drive stimulus to DUT through interface in uvm environment using synopsys vcs tool with uvm 1.1d pkg. 

I got error as,  error: uninitialized virtual interface object   at time 0 in file driver.sv line 29.

Plz help me out with this error

[chr_sue]

Your verification environment is not a UVM environment. It is a Verilog testbench written in SV.

You do not construct it in accordance with the UVM rules.

Your driver is never going through the build_phase, because you are calling in your toplevel module simply the constructor of your driver. But this call is not related to any virtual interface.

[Abdul Razak H S]

Thank you chr_sue.