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Confused between Definitions

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Per my understanding, UVC can be two types, module UVC and interface UVC, module UVC is usually passive for checkers/monitors/scoreboards of a DUT, and interface UVC is usually active for stimulus driving. And for agent, usually a UVC can have several agents inside, for example, a AHB UVC can have master agent and slave agent both inside.


Hope that be helpful.

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SA ,,, Another question please,, could I define more that port object of the same type in the same class like those ?


uvm_anaylsis_port #(dataObject) mon_coll_port;


uvm_anaylsis_port #(dataObject) mon_rest_port;



if yes ,, why UVM Developer develop " `uvm_anaylsis_imp_decl()" macros utility ,,, 


Thanks a lot in advance

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  • 2 weeks later...

SystemVerilog does not allow 'function overloading' like C++. Suppose I have a class A with a function write as follows:


class MyClass

    function void write(input T1 value); ... endfunction

    function void write(input T2 value); ... endfunction // ***ERROR*** Not allowed to have two 'write' functions in same class (no overloading allowed)



Instead you should have:


class MyClass

    function void write_T1(input T1 value); ... endfunction

    function void write_T2(input T2 value); ... endfunction // OK, different name


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Hi Hany,

 just returning to your original question yes you can have two analysis *ports* in a class. However as David explained, there is a problem if you try to have two analysis *imp*s in a class. Because then you need two functions called write() (the function implementations), which only differ in argument type - which is not allowed.


What the decl_imp macros do is declare a kind of wrapper class, which implements write(), and then automatically forwards write to a function with a different name. You can then write the two functions with different names as that doesn't require overloading.


You might find it helpful to look at the macro itself to see exactly what it does,




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The interface UVC and module UVC is difference in this way:


Interface UVC -- develop for designated PROTOCOL and can be used in verification of any device which uses that protocol.

Module UVC   -- Designs for Device Specific verification logic.


Now, let me try to answer part of this question which I think David and apfitch miss.

     uvm_analysis_port #(dataObject) mon_coll_port;

     umv_analysis_port #(dataObject) mon_rest_port;


YES.  You can use these ports if the implemented write() function is in two separate classes

e.g:  myclass_mon_coll_port and myclass_rest_port


Let's say that in the run_phase() you have these lines:

      mon_coll_port.write(dataObject);      // use write() func in myclass_mon_coll_port

      mon_rest_port.write(dataObject);     // use write() func in myclass_mon_rest_port     


If your purpose is to have the implemented write() in the same class then refer to the answers

from David and apfitch.




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  • 8 years later...

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