named event to trigger between class and module

[ljepson74]

We (as an industry) normally use virtual interfaces to communicate between the module 'world' and the class 'world' of SystemVerilog.  Right?**

 

Can anyone comment on the use of events (named events) for class<-->module communication?  Good?  Bad?  Gothchas?

 

Scenario: A test wants to send a signal (trigger) to the top (where the DUT is instantiated).

Creating a 1b interface to transmit this trigger seems like overkill, but that is what I did.  I had some trouble triggering on an event between module and class. Hierarchy problems.  I did not try passing the event thru the config_db - if that even makes sense (is possible).

 

**Correct me if I'm wrong, but that's the way I see it.  I'm sure the UVM base class has a sea of code that I don't understand.

 

[ljepson74]

We hacked around with this tonight @ http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley

 

Here is the code.   I think the uvm added to some confusion for me.   Maybe tomorrow I'll replace the interface I used.

// From SVSC meetup, 2015 July 20
// Some code we hacked around with.
// Trying to get event to trigger between module and class.
// Play: 
//   Swap A1 and A2. 
//   Switch the locations of the initial blocks, so order compiler
//    encounters them differs.
//   Comment out/in B1, to adjust the triggering of the event

class event_holder;
   event class_e;

   function new();
      $display(" pre trigger.");      
      ->$root.top.top_e;    //or even just ->top.top_e;
      $display(" post trigger.");      
   endfunction
endclass : event_holder


module top;
   event top_e;

   initial begin
      event_holder m_event_holder;
      $display(" Start ** ** **.");
      #1;  //B1
      m_event_holder=new();      
      #55;
      //->top_e;
   end

   initial begin
      $display(" pre event.");
      @top_e;                   //A1
      //wait(top_e.triggered);  //A2
      $display(" post event.");
   end
endmodule

[tudor.timi]

Instead of creating your own event_holder class, you should just use uvm_event. It does the same thing and has some extra goodies. You could pass this through your config DB.

[ElenaHammari]

Hi! Does anyone have a good idea of how to synchronize the other way around, i.e. make UVM class to wait for a system verilog event in a DUT module?

module DUT

event  done;

...

endmodule

class test extends test_base;

   virtual task run_phase(uvm_phase phase);
      wait($root.DUT.done); // not working
      ...
   endtask : run_phase

endclass

 

[David Black]

How about basic Verilog syntax?

@($root.DUT.done);

and