Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

[DV-E]

In below test case, I ran into an infinite-loop.  Based on uvm reference, it is legal code.   I understand where the issue comes from, but wondering if it is a known issue in UVM IEEE.  

 

[

//skipped driver and others...  

import uvm_pkg::*;
`include "uvm_macros.svh"

// Tranx
//*********************************
class seqItem extends uvm_sequence_item;
   `uvm_object_utils(seqItem)
   function new(string name = "seqItem");
     super.new(name);
   endfunction
endclass

// bus seq
//********************************
class seqr extends uvm_sequencer#(seqItem);
  `uvm_component_utils(seqr)
   function new(string name ="seqr", uvm_component p = null);
     super.new(name, p);
   endfunction
endclass

// vir sequencer
//*********************************************
class vseqr extends uvm_sequencer;
  `uvm_component_utils(vseqr)
   seqr    sqr;
   function new(string name ="vseqr", uvm_component p = null);
     super.new(name, p);
   endfunction
   function void build_phase(uvm_phase phase);
    sqr = seqr::type_id::create("sqr", this);
   endfunction
endclass

// sequence
//************************************
class seq extends uvm_sequence;
  `uvm_declare_p_sequencer(vseqr)
   seqItem   item;
   vseqr vsqr;
  `uvm_object_utils(seq)
   function new(string name ="seq");
     super.new(name);
   endfunction
         
   task body;
    `uvm_create(item, vsqr.sqr);         // create item on bus sequencer, it is legal code.    
     start_item(item);
     finish_item(item);
   endtask
endclass


//*********************************
class test extends uvm_test;
  `uvm_component_utils(test)
   seq     sq;
   vseqr vsqr;
  function new(string  name ="test", uvm_component p = null);
    super.new(name, p);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    sq = seq::type_id::create("sq");
    vsqr =vseqr::type_id::create("vsqr", this);
    sq.vsqr = this.vsqr;
   endfunction

  task run_phase( uvm_phase phase);
    phase.raise_objection(this);
    fork 
      sq.start(vsqr);   
      #2;
    join_any
    //vsqr.sqr.stop_sequences();   // ok  
    vsqr.stop_sequences();
    vsqr.sqr.stop_sequences();     // it goes forever-loop 
    phase.drop_objection(this);
endtask
endclass

module top;
  test t=new();
  initial 
    run_test();
endmodule

 

[chr_sue]

You have a few weaknesses in your code:

(1) Your class seq seems to be a virtual sequence, because you do not parameterize it for a ceratin seq_item. In the body task you are creating seq_items.

(2) You are declaring vsqr as p_sequencer and at thge same time you are using it as virtual sequencer.

(3) If you do not have  a forever loop in your sequence it comes always to its end. It is useless to stop sequences with the corresponding commands.

(4) run_test instantiates your test implicitly  You do not have to construct it explicitely.

(5) sequences are transient objects and no components. They will not be constructed in the build_phase.

I guess your problem comes from calling stop_sequences.

[DV-E]

Thanks for your response and advice.  It is not a full test bench,  it is only a test case to demo the issue.  As i mentioned at the first line of code

 // skipped driver and others. 

`uvm_declare_p_sequencer(xx) is a leftover for my debugging, it should not be there, but it has no effects anyway.  

The issue is from below while-loop

function void uvm_sequencer_base::stop_sequences();
  uvm_sequence_base seq_ptr;

  seq_ptr = m_find_sequence(-1);
  while (seq_ptr != null)
    begin
      kill_sequence(seq_ptr);
      seq_ptr = m_find_sequence(-1);
    end
endfunction

I would like to know in my test case, the usage of uvm_create(item, seqr) along with below two stop_sequences() is incorrect? or there should be an enhancement in UVM IEEE. 

       vsqr.stop_sequences();

       vsqr.sqr.stop_sequences();

Thanks

 

 

 

[Georgegg]

Did you ever resolve this?

I believe I'm running into the same issue.