is it possible to start seqences which run on different clock?

[gengjie]

I have a UVM TB with  a agent to config the registers of the dut. and another 4 agents for packet transaction。

In my test, I have to write the register first and start the packet transaction later on. the code of the sequence look like:

 

//////////

virtual task body();

`uvm_do_on(my_norm_reg_seq, p_sequencer.reg_sqr); //on clk1
repeat(sent_cnt)
begin
fork
`uvm_do_on(incr_send_pkt_seq_0, p_sequencer.eth_sqr_0); //drvs on clk1
`uvm_do_on(incr_send_pkt_seq_1, p_sequencer.eth_sqr_1); //drvs on clk1
`uvm_do_on(incr_send_pkt_seq_2, p_sequencer.eth_sqr_2); //drvs on clk2
`uvm_do_on(incr_send_pkt_seq_3, p_sequencer.eth_sqr_3); //drvs on clk2
join
end
endtask : body

///////////

 

if I use all these agents which send the sequence with the same clock, everything is ok.

if I use 2 packet agents and the register agent with clk1, the other 2 agents with clk2, the transaction with clk1 work fine, but the transaction with clk2 is not working.

 

if I use 2 packet agents and the register agent with clk2, the other 2 agents with clk1, the transaction with clk2 work fine, but the transaction with clk1 is not working.

 

if I comment out the norm_reg_seq line without configure the register on clk1, the TB will send packet on both clk1 and clk2 in each port correctly.

 

I doubt if the UVM can switch the clock of the sequences automatically. or is there anything I should tell UVM to do this? does any one really tried to use different clocks for the sequences which executed one after another?

[nirmish]

I did this long back, I had modeled two agents ( one for RX path and one for TX path). and an APB VIP for configuring registers ( on some different clk)  I think I did not see any issue in that.

 

does your driver is common for all these sequencers ? if no then I don't see any issue there, it should work.

 

Please send an error you are getting, if any

[David Black]

UVM itself knows nothing about clocks. UVM is a transaction level methodology. It is the drivers that deal with clocks and pin-level timing concerns. Each driver is connected to a sequencer (1 to 1 relationship) within an agent. So I have to assume that your sequencers are commented to reflect the fact that their respective drivers deal with the respective clocks. So if you send a transaction to eth_seqr0, then it will use the timing dictated by the driver connected to eth_seqr0 (? possibly eth_drvr0 ?).

 

Your answer most likely lies in the hardware interface, and really has very little to do directly with UVM.

 

Of course it is possible that clock driving information is embedded in the transaction items themselves for interpretation by the drivers; however, I doubt it since that would probably not be the best from a design point of view.