Jump to content

Clocking blocking driving very first data half the negedge clock only

Recommended Posts



    clocking drv_cb @(posedge clk);
        output data;
        output sop;
        output eop;

task rbus_driver::drive_one_pkt(rbus_data trans);
        vif.sop      <= 1'b1;
        vif.deop    <= 1'b1;
        vif.data     <= trans.bytes;

above is my scenario in this very first data driving starts at negedge of the clk. from second it starts driving from posedge of the clock i don't know why? in the env i have 2 drivers similiar other one driveing perfect from posedge of clk


please any body know why? 

Link to comment
Share on other sites

Did you mean to write

task rbus_driver::drive_one_pkt(rbus_data trans);
        vif.drv_cb.sop      <= 1'b1;
        vif.drv_cb.deop    <= 1'b1;
        vif.drv_cb.data     <= trans.bytes;


Two basic rules about using clocking blocks.

  1. If you plan to use clocking block variables, only use those variables, not the raw, unclocked versions of those variables.
  2. Make sure a clocking block sample or drive statement is synchronized to the clocking block event.
Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...