Clocking blocking driving very first data half the negedge clock only

[Mahnedra]

Hi

 

    clocking drv_cb @(posedge clk);
        output data;
        output sop;
        output eop;
    endclocking
 

task rbus_driver::drive_one_pkt(rbus_data trans);
        vif.sop      <= 1'b1;
        vif.deop    <= 1'b1;
        vif.data     <= trans.bytes;
     @vif.drv_cb;
end
 

above is my scenario in this very first data driving starts at negedge of the clk. from second it starts driving from posedge of the clock i don't know why? in the env i have 2 drivers similiar other one driveing perfect from posedge of clk

 

please any body know why? 

[dave_59]

Did you mean to write

task rbus_driver::drive_one_pkt(rbus_data trans);
     @vif.drv_cb;
        vif.drv_cb.sop      <= 1'b1;
        vif.drv_cb.deop    <= 1'b1;
        vif.drv_cb.data     <= trans.bytes;

end

Two basic rules about using clocking blocks.

1. If you plan to use clocking block variables, only use those variables, not the raw, unclocked versions of those variables.
2. Make sure a clocking block sample or drive statement is synchronized to the clocking block event.