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gengjie

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  1. I have a UVM TB with a agent to config the registers of the dut. and another 4 agents for packet transaction。 In my test, I have to write the register first and start the packet transaction later on. the code of the sequence look like: ////////// virtual task body(); `uvm_do_on(my_norm_reg_seq, p_sequencer.reg_sqr); //on clk1 repeat(sent_cnt) begin fork `uvm_do_on(incr_send_pkt_seq_0, p_sequencer.eth_sqr_0); //drvs on clk1 `uvm_do_on(incr_send_pkt_seq_1, p_sequencer.eth_sqr_1); //drvs on clk1 `uvm_do_on(incr_send_pkt_seq_2, p_sequencer.eth_sqr_2); //drvs on clk2 `uvm_do_on(incr_send_pkt_seq_3, p_sequencer.eth_sqr_3); //drvs on clk2 join end endtask : body /////////// if I use all these agents which send the sequence with the same clock, everything is ok. if I use 2 packet agents and the register agent with clk1, the other 2 agents with clk2, the transaction with clk1 work fine, but the transaction with clk2 is not working. if I use 2 packet agents and the register agent with clk2, the other 2 agents with clk1, the transaction with clk2 work fine, but the transaction with clk1 is not working. if I comment out the norm_reg_seq line without configure the register on clk1, the TB will send packet on both clk1 and clk2 in each port correctly. I doubt if the UVM can switch the clock of the sequences automatically. or is there anything I should tell UVM to do this? does any one really tried to use different clocks for the sequences which executed one after another?
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