thuvm Posted February 7, 2014 Report Share Posted February 7, 2014 Hi All, I have a basic SystemC TB which has VHDL DUT and some systemC TB components instantiated. Now I want to build a SystemVerilog UVM TB on top of this systemC TB. 1. Is it possible to do this? 2. How to access systemC TB components (like systemC threads, systemC variables & systemC events, etc..) from SystemVerilog TB? Please help to clarify this basic query. Thanks in advance! Quote Link to comment Share on other sites More sharing options...
apfitch Posted February 7, 2014 Report Share Posted February 7, 2014 To connect UVM and SystemC, depending on your toolset, you could try Mentor's UVM Connect (which they say should work on all tools); Synopsys TLI; or Cadence UVM-SC. regards Alan Quote Link to comment Share on other sites More sharing options...
David Black Posted February 7, 2014 Report Share Posted February 7, 2014 Likely as not you will also need to reword your SystemC TB somewhat (or perhaps even remove to be replaced by SystemVerilog driven version). What I mean is that SystemVerilog/UVM probably needs to be able to control the SystemC model. At very least, there needs to be a way to halt and progress time externally. Another approach is to have the SystemVerilog issue commands to the fabric. Quite a lot of this depends on exactly what you are modeling. Quote Link to comment Share on other sites More sharing options...
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