UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. Urgent Help: Connecting VHDL port with SV Interface ??

   By desperado, November 25, 2010
   • 4 replies
   • 7.7k views
   • 
   • mrmikehicks
   • July 20, 2011

2. Question for array of class

   By yyn, July 19, 2011
   • 2 replies
   • 2.3k views
   • 
   • uwes
   • July 20, 2011

3. Controlling the slave sequence response from the test case

   By pradeey, July 15, 2011
   • 3 replies
   • 3.8k views
   • 
   • adielkhan
   • July 18, 2011

4. uvm_packer status

   By Kinjal, July 14, 2011
   • 4 replies
   • 1.8k views
   • 
   • Kinjal
   • July 15, 2011

5. How to run multiple tests

   By qwerty123, July 15, 2011
   • 2 replies
   • 7k views
   • 
   • adielkhan
   • July 15, 2011

6. Error in registering

   By qwerty123, July 14, 2011
   • 3 replies
   • 2k views
   • 
   • arno
   • July 15, 2011

7. best way to use inst_override on seq_item/sequence

   By krb, July 13, 2011
   • 1 reply
   • 1.3k views
   • 
   • pjigar
   • July 14, 2011

8. [uvm_event] wait_trigger could not be cancelled by disable fork. why?

   By SeanChou, July 12, 2011
   • 5 replies
   • 4.1k views
   • 
   • SeanChou
   • July 14, 2011

9. What Tool Generated the Class Reference?

   By bhunter1972, July 8, 2011
   • 1 reply
   • 2k views
   • 
   • uwes
   • July 11, 2011

10. Is it there any tools can generate the register file for both RTL and UVM?

    By enchanter, July 6, 2011
    • 2 replies
    • 1.7k views
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    • uwes
    • July 8, 2011

11. Is this a bug in uvm?

    By mpeer, April 8, 2011
    • 6 replies
    • 2.9k views
    • 
    • janick
    • July 7, 2011

12. how to set drain time in UVM-1.1?

    By qinhailiang, July 7, 2011
    • 2 replies
    • 8.1k views
    • 
    • qinhailiang
    • July 7, 2011

13. Problem with *_report_*_action and UVM_COUNT

    By ifpk454, July 5, 2011
    • 5 replies
    • 3.5k views
    • 
    • ifpk454
    • July 6, 2011

14. Question for uvm_analysis_port usage

    By yyn, July 3, 2011
    • 3 replies
    • 4.1k views
    • 
    • uwes
    • July 5, 2011

15. Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_drain_time

    By qinhailiang, July 5, 2011
    • 2 replies
    • 3.2k views
    • 
    • qinhailiang
    • July 5, 2011

16. uvm_mem get method?

    By scnix1, July 1, 2011
    • 1 reply
    • 2.4k views
    • 
    • janick
    • July 4, 2011

17. [uvm_mem_mam] how to allocate alligned memory? for example 16 bytes alligned?

    By SeanChou, July 4, 2011
    • 1 reply
    • 2.8k views
    • 
    • SeanChou
    • July 4, 2011

18. uvm base class first extensions

    By naveeng, June 28, 2011
    • 3 replies
    • 1.5k views
    • 
    • uwes
    • July 1, 2011

19. Register field access issue

    By morningyue, June 28, 2011
    • 1 reply
    • 1.9k views
    • 
    • janick
    • June 29, 2011

20. register model and adressh mismatch in mapping

    By fduthu, June 20, 2011
    • 1 reply
    • 1.6k views
    • 
    • janick
    • June 28, 2011

21. Question about "uvm_reg_sequence"

    By yyn, June 24, 2011
    • 1 reply
    • 3.2k views
    • 
    • janick
    • June 28, 2011

22. burst_ write in a memory

    By paul, June 27, 2011
    • 1 reply
    • 1.4k views
    • 
    • SeanChou
    • June 27, 2011

23. Virtual Sequence not work in some condition with uvm1.1

    By aaron626, June 14, 2011
    • 4 replies
    • 4.9k views
    • 
    • uwes
    • June 24, 2011

24. UVM Reg backdoor Read vs. Peek

    By sreekrish, June 8, 2011
    • 1 reply
    • 11.6k views
    • 
    • svarun
    • June 24, 2011

25. Unable to use big_endian field if object of uvm_packer is not accessible

    By Vishwanath, June 21, 2011
    • 0 replies
    • 1.5k views
    • 
    • Vishwanath
    • June 21, 2011