UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. UVM components in VMM enviroments.

   By knoecksj, August 15, 2011
   • 2 replies
   • 3.7k views
   • 
   • Roman
   • August 31, 2011

2. Question for mirror() function in uvm_reg

   By yyn, August 24, 2011
   • 6 replies
   • 11.8k views
   • 
   • kiranbhaskar
   • August 31, 2011

3. Indirect Memory access issue

   By paul, August 30, 2011
   • 1 reply
   • 1.4k views
   • 
   • janick
   • August 30, 2011

4. How to use the predict method using explicit monitoring?

   By kiranbhaskar, August 22, 2011
   • 0 replies
   • 1.1k views
   • 
   • kiranbhaskar
   • August 22, 2011

5. uvm_sequence_library and the use of the macro utils in the source code comments....

   By ifpk454, August 18, 2011
   • 4 replies
   • 2.4k views
   • 
   • ifpk454
   • August 19, 2011

6. How to control the print verbosity of print function?

   By agump, August 18, 2011
   • 2 replies
   • 2.2k views
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   • agump
   • August 19, 2011

7. Parameterized Virtual Interface

   By dudi, August 16, 2011
   • 10 replies
   • 7.8k views
   • 
   • pratta
   • August 19, 2011

8. Register package factory registration

   By hmeiners, July 18, 2011
   • 4 replies
   • 2.4k views
   • 
   • uwes
   • August 18, 2011

9. Sequence stops suddenly

   By johannes.walter, July 4, 2011
   • 3 replies
   • 1.5k views
   • 
   • ashu_83
   • August 17, 2011

10. uvm_reg_access_seq can't test registers with RO fields. Why?

    By jeff.schroeder, August 15, 2011
    • 0 replies
    • 2.5k views
    • 
    • jeff.schroeder
    • August 15, 2011

11. Cloning on dynamic objects

    By Kinjal, August 8, 2011
    • 3 replies
    • 3.6k views
    • 
    • jadec
    • August 11, 2011

12. include_coverage() scope question.

    By mszabo, August 5, 2011
    • 2 replies
    • 3k views
    • 
    • janick
    • August 11, 2011

13. [Help] An compile error encountered when I run the examples in "uvm-1.0p1"

    By chx, April 17, 2011
    • 4 replies
    • 5.3k views
    • 
    • loki
    • August 10, 2011

14. uvm_config_db::dump() output shows only '?' for values

    By ejessen, August 5, 2011
    • 1 reply
    • 5.6k views
    • 
    • uwes
    • August 8, 2011

15. UVM with MCU/CPU

    By chenyong, August 3, 2011
    • 6 replies
    • 4k views
    • 
    • chenyong
    • August 5, 2011

16. uvm_sequence_library - anyone using this?

    By ifpk454, May 25, 2011
    • 9 replies
    • 3k views
    • 
    • uwes
    • August 3, 2011

17. Random Stability when changing Verbosity

    By zinn, May 12, 2011
    • 21 replies
    • 6.9k views
    • 
    • uwes
    • August 3, 2011

18. Null object error from uvm_config.sv

    By suleesh, July 26, 2011
    • 2 replies
    • 8.8k views
    • 
    • Bart
    • August 2, 2011

19. backdoor access for RC (Clear on read) register

    By ramkodanda, July 29, 2011
    • 1 reply
    • 2.6k views
    • 
    • janick
    • August 2, 2011

20. base class for reference model in DUT Verification environment

    By Nirav Patel, July 27, 2011
    • 3 replies
    • 2.7k views
    • 
    • Praveen Chenna
    • July 28, 2011

21. Can we have multiple verbosity levels?

    By qwerty123, July 25, 2011
    • 1 reply
    • 1.1k views
    • 
    • arno
    • July 25, 2011

22. using set type override to replace parametrzed class

    By Neel.011, July 20, 2011
    • 4 replies
    • 4.1k views
    • 
    • dave_59
    • July 22, 2011

23. uvm_reg::get()

    By nmoseley, July 20, 2011
    • 1 reply
    • 2.6k views
    • 
    • janick
    • July 21, 2011

24. UVM 1.0p1 virtual sequencer.

    By venravi, July 19, 2011
    • 2 replies
    • 1.7k views
    • 
    • janick
    • July 21, 2011

25. uvm_reg_mem_hdl_paths_seq

    By paul, July 18, 2011
    • 1 reply
    • 1.8k views
    • 
    • janick
    • July 21, 2011