register model and adressh mismatch in mapping

[fduthu]

hello,

I have a register model describing register with various size 16bits, 32 bits or 64 bits with a 16 bits bus interface

Inside the build of my uvm_reg_block I have :

//define default map and add reg/regfiles

default_map = create_map("default_map", 'h0, 4, UVM_BIG_ENDIAN, 0);

default_map.add_reg(reg_name1, 'h0, "RW");

default_map.add_reg(reg_name2, 'h1, "RW");

default_map.add_reg(reg_name3, 'h3, "RW");

then if I used regmodel.print() function inside my environment I got the following result :

# ---------------------------------------------------------------------------------------

# Name Type Size Value

# ---------------------------------------------------------------------------------------

# regmodel VW_block - @470

# reg_16bits VW_reg_16bits - @472

# dd uvm_reg_field ... RW reg_16bits[15:0]=16'h0000

# reg_32bits VW_reg_32bits - @474

# dsad uvm_reg_field ... RW reg_32bits[31:0]=32'h00000000

# reg_64bits VW_reg_64bits - @476

# dsd uvm_reg_field ... RW reg_64bits[63:0]=64'h0000000000000000

# default_map uvm_reg_map - @484

# endian ... UVM_BIG_ENDIAN

# effective sequencer apb_sequencer ... env.rbus.sqr

# reg_16bits VW_reg_16bits ... @472 +'h0

# reg_32bits VW_reg_32bits ... @474 +'h1

# reg_64bits VW_reg_64bits ... @476 +'h4

# ---------------------------------------------------------------------------------------

I don't understand why my 64 bits register has an offset of 4 as in the regmodel it is set as 3.

I am using uvm1.1.

thanks in advance

[janick]

Looks odd. Might be related to address granularity.

Can you provide a more complete testcase? There is not enough information here to identify the cause.