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krb last won the day on October 7 2016

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  1. Thanks for the prompt reply and helpful suggestion. A small correction for your suggestion, in case anyone looks at this thread for help. The second vlogan should include the uvm src path: vlogan -full64 -work work -sverilog +incdir+${UVM_HOME}/env/uvm-1.1 -f ${filelist} -l compile.vcslog
  2. Hi, Trying to compile my mixed vhdl/ SV-UVM code with vcs. dut is in vhdl and uvm testbench is in SV. I am using the multi-step analyse/eloborate method and have problem here. 1) vhdlan -full64 -work work -file ${vhdl_f} -l compile.vcslog -- works fine 2) vlogan -ntb_opts uvm-1.1 -full64 -work work -sverilog -lca -f ${filelist} -l compile.vcslog reports this error: Error-[sV-LCM-PND] Package not defined my_pkg.sv, 141 my_pkg, "uvm_pkg::" Package scope resolution failed. Token 'uvm_pkg' is not a package. Originating module 'my_pkg'. Move package definition before the use of th
  3. Hi, A question along the same line, how can my test know when it is stopped due to timeout, from a previous timeout setting (either using the function or from cmdline) ? Thanks, krb
  4. Hello Good folks at Cadence, I am trying to use "+UVM_TIMEOUT=200,YES" on the command line. I am not sure this works. There is no confirmation UVM_INFO statement printed out as the "uvm_root.svh" code suggests should be doing. I am using ml_uvm and invoke my test with -uvmtest argument. Any suggestions on how to get this to work ? Also any idea on what timeunit will the timeout value be applied at ? Many thanks, karthik.
  5. I noticed that I can't use any thing other than a == with real data type in the constraints block with IUS. Is this a limitation in SV LRM ? I apologize if this is going into simulator specific details. If you think I should start a new thread in simulator specific forums, let me know.
  6. I wasn't mentioning to the use of logic data type, but to logic in declaring class members. I also changed your "logic [7:0] my_data" to bit type because the rand modifier only works on 2-state data types (bit). You don't have to use the rand modifier, as I did in the example. The constraint block will have no meaning without the rand.
  7. No You cannot declare variables like this at run time. NOTE: you cannot use logic to declare class members. You could use `defines to declare variables at compile time eg: `define MY_COLOR_IS_RED 1 class my_class; color_type my_color; // Only when my_color is RED, I want this class to have another field called my_data `ifdef MY_COLOR_IS_RED rand bit [7:0] my_data; `endif endclass Not sure what your intentions are here, but this may be enough for you. class my_class; color_type my_color; rand bit [7:0] my_data; constarint c_my_data_valid_only_
  8. Hi Uwe, Thanks a lot for the links, I now understand how to make best use of Natural Docs. And it seems pretty flexible and powerful at the same time. A final question, is there a way to get pdf from natural docs. I ask because, the UVM doc has a pdf that is similar to the html docs. Or do you convert the html docs to pdf ? Thanks again, krb
  9. Hi Uwes, After a bit of googling, I found that I need to add these lines to this file Config/Languages.txt. Is this it or do I need any more changes to natural docs ? Thanks, krb. Language: SystemVerilog Extensions: sv svh Line Comment: // Block Comment: /* */ Package Separator: :: Enum Values: Global Class Prototype Ender: ; Function Prototype Ender: ; Variable Prototype Ender: ; Method Prototype Ender: ; Line Extender: \
  10. Hi uwes, Thanks for the reply. Does naturaldocs has inbuild support for SV ? or do I need an additional filter script of some kind ?
  11. Hi, Sorry for a non-technical post. How is UVM base class documented ? I see the comments in UVM base class have a lot in common with the UVM reference documents. So I was wondering if doxygen or something similar was used. We would like to use something similar. Thanks, krb
  12. That's one way of doing things. I was hoping there would be a more direct way of converting real/short_real data type into an ieee 32 encoded floating point value. eg: constraint c_real { (float_in_bits_32 == convert_to_bits(3.2)); } or constraint c_real { (float_in_bits_32 >= convert_to_bits(3.2)); (float_in_bits_32 <= convert_to_bits(100.0)); } This way of constraining is more readable and direct.
  13. Hi gabi, Thanks for the advice. I found about the switch you mentioned after I posted the question, with some help from Cadence support. I can confirm that this switch works. krb
  14. Hello, I am migrating my uvm1.0ea code to uvm1.1. I use ml_uvm to communicate with sysc models. Using uvm1.0ea (and the ml_uvm that came with it) worked just fine. Now when I migrated by code to uvm1.1, I get this error: UVM_FATAL @ 55: reporter [XMAXSTRSZ] Packed ML UVM/OVM transaction size exceeded maximal stream size This is happening on the first transaction that is sent to sysc. When I disable this transfer of transaction from SV to sysc, my uvm1.1 test envinormant works as intended, i.e, all sequences finish and test finishes as I would expect. So to debug further, I sta
  15. I think the benefit of using using sequences/virtual_sequences is that they could be reused in other sequences. I am not sure if you can reuse a uvm_test (derived components). I partly see the point in your question. At the moment for my test envinorment, there is a one to one correspondence for a uvm_test to a top_level sequence.
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