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  1. I know it work if it replaced with + read_byte_seq0.start(p_sequencer.seqr1,this); I said in this thread 'uvm_do_on_with(....)' and 'seq.start(seqr, this )' all works. the `uvm_send(seq) not work, but this work in UVM1.0p1.
  2. Could you please run the ubus example? uvm_create_on in virtual sequence not work. test case name: test_2m_4s_azhang The virtual sequence test_2m_4s_azhang_vseq used in this testcase. // This way, can work `uvm_do_on_with(read_byte_seq0, p_sequencer.seqr1, {read_byte_seq0.transmit_del == 0; }) // This way can not work `uvm_create_on(read_byte_seq0, p_sequencer.seqr1) assert(read_byte_seq0.randomize() with {read_byte_seq0.transmit_del == 0; }) `uvm_send(read_byte_seq0) You can try this simulation with command: % make -f Makefile.ius The simulation can not exit normally.
  3. Currently we download UVM1.1 and run simulation with it in our project, some tests passed with uvm1.0p1, but failed with uvm1.1. We have used three methods to issue sequence in virtual sequence. Below method1 and method2 work, method3 not work(can't get item in driver). method1: `uvm_do_on_with(....) method2: step1: wr_seq = new ("test_seq") step2: randomize wr_seq step3: wr_seq.start(p_sequencer.wr_seqr) method3: step1: `uvm_create_on(wr_seq, p_sequencer.wr_seqr) step2: randomize wr_seq step3: `uvm_send(wr_seq)
  4. Can anyone help me? In virtual sequence, it works if the first parameter for ovm_create_on is sequence. But if the first parameter is sequence_item, it can not work. Maybe it is a bug. (IUS92.36, UVM1.0p1) virtual task body(); repeat(1) begin $display("Start Create"); `uvm_create_on(seq, p_sequencer.seqr) $display("Start Randomize"); assert (seq.randomize()); $display("Start Send"); `uvm_send(seq) $display("Trans Complete"); $display("Start Create2"); `uvm_create_on(trans, p_sequencer.seqr) $display("Start Randomize2"); assert(trans.randomize() with { trans.addr == 'h1000; trans.read_write == READ; trans.size == 1; trans.error_pos == 1000; trans.transmit_delay == 10; } ) $display("Start Send2"); [COLOR="Red"] `uvm_send(trans) // Never returned from this macro ERROR[/COLOR] $display("Trans Complete2"); get_response(rsp); end endtask See the attached code, run testcase test_read_modify_write_2 with the following command: make -f Makefile.ius
  5. In testcase: function void build_phase(uvm_phase phase); super.build_phase(phase); // Enable slaves uvm_config_db#(uvm_active_passive_enum)::set(this, "tb_inst", "en_slave*", UVM_PASSIVE); uvm_config_db#(uvm_active_passive_enum)::set(this, "tb_inst", "en_slave_cpu_rw1", UVM_ACTIVE); ... In tb_top, I have defined en_slave_cpu_rw1,en_slave_cpu_rw2,en_slave_cpu_rw3,en_slave_cpu_rw4 Using above configuation, expected: en_slave_cpu_rw is UVM_ACTIVE, other is UVM_PASSIVE; But to check the run log file, ALL en_* are UVM_PASSIVE If codes like this: set_config_int("ocp_tb_inst", "en_slave*", UVM_PASSIVE); set_config_int("ocp_tb_inst", "en_slave_cpu_rw1", UVM_ACTIVE); Only the en_slave_cpu_rw1 is UVM_ACTIVE, and others are UVM_PASSIVE. By the way: In build phase of tb_top, I have used uvm_config_db::get.. If not using them, we can not set en_slave* by group, only one by one. virtual function void build_phase(uvm_phase phase); super.build_phase(phase); void'(uvm_config_db#(uvm_active_passive_enum)::get(this, "", "en_slave_cpu_rw1", en_slave_cpu_rw1)); void'(uvm_config_db#(uvm_active_passive_enum)::get(this, "", "en_slave_cpu_rw2", en_slave_cpu_rw2)); void'(uvm_config_db#(uvm_active_passive_enum)::get(this, "", "en_slave_cpu_rw3", en_slave_cpu_rw3)); void'(uvm_config_db#(uvm_active_passive_enum)::get(this, "", "en_slave_cpu_rw4", en_slave_cpu_rw4)); So I think the UVM code should be improvemented.
  6. you can run the ubus example in the UVM kit 1.0. irun.log we can not see the default sequence, so I don't know if we have configured the default sequence properly. In test case, using uvm_config_db method: code: uvm_config_db#(uvm_object_wrapper)::set(this,"*.ubus0.masters[0].sequencer.main_phase", "default_sequence", loop_read_modify_write_seq::type_id::get());
  7. class TB_env extends uvm_env; int test = 0; int test1 = 0; int test2 = 0; `uvm_component_utils_begin(tb_axi_ovc_self_loop) `uvm_field_int (test, UVM_ALL_ON) `uvm_field_int (test1, UVM_ALL_ON) `uvm_field_int (test2, UVM_ALL_ON) `uvm_component_utils_end virtual function void build_phase(uvm_phase phase); super.build_phase(phase); [I][B] void'(get_config_int("test", test)); void'(get_config_int("test1", test1)); void'(get_config_int("test2", test2)); [/B][/I] endfunction endclass Can anyone tell me why it work after adding these three lines? I don't think we must add these lines, at least we have not these code in OVM, but OVM code can work.
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