SeanChou

yes, I agree with you that the on-the-fly reset idea could be implemented by only sequence without any phase jump. However, my situation now is the 2 existing environments already implemented the on-the-fly reset by using phase jump from main_phase to pre_reset_phase(). In integrated environment, The phase jump on-the-fly reset seems still works veritcally, Besides the 2 interfaces are reseted in same time (i guess because they works in the phase in default), for the purpose the separte them temporally. I try to separate them into different domains. Still thanks for your suggestion, could you let me know the reason and we may not to implment on-the-fly reset by phase jump in the future.

Hi, UVM Exports, I am writing a test to put 2 uvm_env A and B together and hope to separate them in different domains. I hope to give each environment his own run_phases time line. how could I do this? thanks! hope you could provide some hints or several lines of code for my reference. thanks a lot!

mainly for bug fixed for 1.1, should be transparent to users. http://www.accellera.org/downloads/standards/uvm/uvm-1.1c_release-notes.txt

Hi UVM Connect exports, As title, druing developing, we sometimes hope to replace std::vector with __gnu_debug::vector for debugging purpose. However, this replacement makes uvmc to encounter a fatal error as below (with Questa 10.1) ** Fatal: (SIGABRT) Bad handle or reference ... Fatal error in Module uvmc_pkg at ....uvmc2.2/src/connect/sv/uvmc_tlm1.sv line 36 is there any suggestion how to handle this? thanks! insert a std to gnu_debuger converter could help, however, its not convinent any more.

Hi, UVM Connect exports, As title, some existed TLM channels exchanges primitive datas without class wrapped, however, when I connect them to another langange via UVM connect, this problem happnes because the uvmc linvokes new(), which could infer the lhs must be a class object. is the any way I can do besides packaging them with classes? thanks!

Hi UVM connect export, I hope to use tlm_analysis_port in direction SV report to SC (I could only find the other direction in uvmc example) so I try to write my own as following. By printing some message I found the analysis port in SV side has been written, however the SC side write did not be invoked, could some one give some hint to the problem or how to debug it has been connected correctly? (I am new to SC so there could be some stupid mistake, please forgive me if any) thanks! SC: class my_subscriber : public sc_module, public tlm_analysis_if <my_pkt> { virtual void write (const my_pkt &pt) { //... } } int sc_main (int argc, char** argv[]) { my_subscriber sub("sub"); // uvm_connect(sub, "my_ap"); // I modified previous line to following 2 lines // because ambiguous call due to multiple inheritance uvmc_analysis_port<my_pkt> port (sub.name(), "my_ap"); port.bind(cons); sc_start(); return 0; } SV: uvmc_tlm1 #(my_pkt)::connect(uvm_ap, "my_ap");

yes it is exactly the same. thanks a lot for uwes' quick response.

UVM exports, After debug, I thought the second argument (SEQR) missed in "__seq.set_item_context(this);" which implies to set_sequencer = NULL and cause the sequence could not find its sequencer and stop. could some one verify this? thanks! For my case the SEQ_OR_ITEM is an uvm_sequence, I am not sure the same error happens when its an item. `define uvm_rand_send_pri_with(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ begin \ uvm_sequence_base __seq; \ if (!$cast(__seq,SEQ_OR_ITEM)) start_item(SEQ_OR_ITEM, PRIORITY);\ else __seq.set_item_context(this); \ if ((__seq == null || !__seq.do_not_randomize) && !SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send_with action") \ end\ if (!$cast(__seq,SEQ_OR_ITEM)) finish_item(SEQ_OR_ITEM, PRIORITY);\ else __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end

thanks Dave to let me know the OS need to be updated. The issue was fixed after using another machine.

Hi Exports, I hope to run the UVM connect example and in the stage of compiling uvmc pkg. uvmc-2.2/lib $ make uvmc QuestaSim sccom 10.1 compiler 2011.12 Dec 5 2011 ** Error: (sccom-6137) Unsupported "Linux release 4.6" - CentOS release 4.6 (Final). Refer to the QuestSim release notes for a list of supported Linux operating system releases. Is there any workaround for this? thanks!

This problem persists when using -uvm or -uvmhome to replace the original UVM arguments.

Uwes, I got the same error with Synopsys Discovery APB VIP in 10.20s100 or 12.10-p001. TOOL: ncelab 12.10-p001 OS: Linux 2.6.9-67... MESSAGE: sv_seghandler - trapno -1 addr(0x00000017) Any hint how to handle this? thanks!

Any comment?

Hi UVM Reg Exports, In the uvm_reg_field::do_predict() function as following: • why not clear field_val when (acc == “WSRCâ€) after read? • why not set field_val when (acc == “WCRSâ€) after read? is there some reason or simply missing this type? function void uvm_reg_field::do_predict(….) //…………………… UVM_PREDICT_READ: // line 1136 in uvm_reg_field.svh of uvm-1.1b begin uvm_reg_field_cb_iter cbs = new(this); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) begin string acc = get_access(rw.map); if (acc == "RC" || acc == "WRC" || acc == "W1SRC" || acc == "W0SRC") field_val = 0; // (clear) else if (acc == "RS" || acc == "WRS" || acc == "W1CRS" || acc == "W0CRS") field_val = ('b1 << m_size)-1; // all 1's (set) else if (acc == "WO" || acc == "WOC" || acc == "WOS" || acc == "WO1") return; end

Thanks Gordon's good anwser for this, they should be separated into 2 things.