Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_drain_time

[qinhailiang]

We have defined the start_of_simuluation_phase in my testbench class as follow:

function void start_of_simulation_phase(uvm_phase phase);

uvm_test_done.set_drain_time(this, 1000000);

uvm_test_done.set_report_verbosity_level(UVM_HIGH);

endfunction : start_of_simulation_phase

Now, we use the +define+UVM_NO_DEPRECATED switch in Makefile file as follow:

VLOG_OPT = +define+UVM_NO_DEPRECATED

VLOG = vlog \

-timescale "1ns/1ps" \

$(DPILIB_VLOG_OPT) \

$(VLOG_OPT) \

$(OPT_C) \

-mfcu \

-incr \

-suppress 2181 \

+acc=rmb \

-writetoplevels questa.tops \

+incdir+$(UVM_HOME)/src \

$(UVM_HOME)/src/uvm.sv \

But the simulator reports errors as follow:

# vsim +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=sbi_simple_test -do {do wave.do; run -all; q} -l questa.log -sv_lib ../../../../../uvm-1.1/lib/uvm_dpi itdm_tb_top

# ** Note: (vsim-3812) Design is being optimized...

# ** Error: ../../../tb/itdm_ctrl_tb.sv(60): Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_drain_time.

# ** Error: ../../../tb/itdm_ctrl_tb.sv(61): Failed to find 'uvm_test_done' in hierarchical name /uvm_test_done/set_report_verbosity_level.

# Optimization failed

# Error loading design

Would everyone like to tell how to modify it?

[uwes]

hi,

the usage of "uvm_test_done" is deprecated. adding "-define UVM_NO_DEPRECATED" hides all deprecated code from compilation. in order to fix that you should

1. move from using the uvm_test_done objection to an end-of-phase objection

2. probably you also have to change the calls to set_drain_time and set_report_verbosity_level to their UVM10 counterparts.

/uwe

[qinhailiang]

Hi, uwes

if i change the calls to set_drain_time and set_report_verbosity_level to their UVM10 counterparts, how to do it?

Could you like to give an examples to me? thanks a lot for your valuable information!

QIN