UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. uvm phasing

   By Erling, October 13, 2011
   • 19 replies
   • 6k views
   • 
   • Erling
   • November 3, 2011

2. many to one analysis_port to export

   By naveeng, October 25, 2011
   • 14 replies
   • 6.4k views
   • 
   • Erling
   • November 2, 2011

3. constraining data items

   By jao16, October 31, 2011
   • 2 replies
   • 1.1k views
   • 
   • aji.cvc
   • November 1, 2011

4. UVM 1.1 Change of the Agent to Passive does not work as documented

   By frodus, October 27, 2011
   • 3 replies
   • 2.1k views
   • 
   • jadec
   • October 31, 2011

5. When to use create() vs new()

   By jao16, October 27, 2011
   • 1 reply
   • 3.8k views
   • 
   • bhunter1972
   • October 27, 2011

6. m_sequencer -vs- p_sequencer

   By cliffc, October 26, 2011
   • 3 replies
   • 5.2k views
   • 
   • bhunter1972
   • October 26, 2011

7. Comparing Objects with different levels of inheritance

   By calvapete, October 25, 2011
   • 5 replies
   • 3.3k views
   • 
   • Erling
   • October 26, 2011

8. bottom-up or top-down reset

   By shail, October 21, 2011
   • 6 replies
   • 1.7k views
   • 
   • shail
   • October 24, 2011

9. Active test components

   By Erling, October 17, 2011
   • 4 replies
   • 1.6k views
   • 
   • Erling
   • October 21, 2011

10. get_response() with UVM RAL

    By aiyer, October 21, 2011
    • 0 replies
    • 3.6k views
    • 
    • aiyer
    • October 21, 2011

11. [uvm_sequence_library] could I know what sequnce is selected before execute it?

    By SeanChou, October 18, 2011
    • 3 replies
    • 1.5k views
    • 
    • uwes
    • October 20, 2011

12. How to produce a warning for unused config_db "sets" and factory overrides

    By dudi, October 16, 2011
    • 8 replies
    • 3.6k views
    • 
    • dudi
    • October 19, 2011

13. [uvm_mem/uvm_reg_map] Memory burst_write question...

    By clacasse, August 10, 2011
    • 3 replies
    • 5.7k views
    • 
    • clacasse
    • October 18, 2011

14. How to develop scoreboard...???

    By ramesh_balaram, October 11, 2011
    • 1 reply
    • 2.1k views
    • 
    • sdonofrio
    • October 14, 2011

15. Still Having Problem With Bind for VHDL Architecture Signals

    By mrmikehicks, October 7, 2011
    • 4 replies
    • 3.8k views
    • 
    • mrmikehicks
    • October 12, 2011

16. UVM RAL and uvm_reg_data_t: how is X handled?

    By loki, October 11, 2011
    • 2 replies
    • 3.1k views
    • 
    • loki
    • October 12, 2011

17. set_report_verbosity_level

    By chenyong, October 9, 2011
    • 0 replies
    • 2.1k views
    • 
    • chenyong
    • October 9, 2011

18. In UVM Register Layer Primer pdf, what is uvm_reg_reg?

    By loki, September 15, 2011
    • 3 replies
    • 2.4k views
    • 
    • janick
    • October 7, 2011

19. uvm_config_prop

    By chenyong, October 5, 2011
    • 2 replies
    • 1.7k views
    • 
    • chenyong
    • October 6, 2011

20. Question about grab/ungrab for interrupt

    By yyn, September 23, 2011
    • 1 reply
    • 26.1k views
    • 
    • jadec
    • October 4, 2011

21. [uvm_reg] is there any way to control how many byte bus access when read?

    By SeanChou, October 4, 2011
    • 0 replies
    • 1.2k views
    • 
    • SeanChou
    • October 4, 2011

22. DPI support in UVM

    By puneet3010, September 29, 2011
    • 2 replies
    • 1.4k views
    • 
    • puneet3010
    • October 3, 2011

23. Sequence repeating and interrupting

    By gbbrown, September 29, 2011
    • 1 reply
    • 2k views
    • 
    • uwes
    • September 30, 2011

24. Register sequence stops at regmodel.reset();

    By kiranbhaskar, September 29, 2011
    • 0 replies
    • 1.4k views
    • 
    • kiranbhaskar
    • September 29, 2011

25. macro expansion error with minimalistic import

    By loki, September 28, 2011
    • 2 replies
    • 4.4k views
    • 
    • loki
    • September 28, 2011