Question about "uvm_reg_sequence"

[yyn]

Hello,

I have two questions about "uvm_reg_sequence".

In below example, I'd like to use "CLK", which is a signal of "interface my_if" in "my_seq" extended from "uvm_reg_sequence",

How can I connect interface of module to virtual interface of sequence class using "uvm_config_db#(virtual my_if)::get(xxxxx);"

******************************

interface my_if;

logic CLK;

endinterface

module my_top;

import uvm_pkg::*;

`include "uvm_macros.svh"

reg CLK;

my_if mif(.*);

assign mif.CLK = CLK;

class my_seq extends uvm_reg_sequence;

virtual interface my_if vif;

virtual task body();

repeat (10) @(posedge vif.CLK);

endtask

endclass

class my_test extends uvm_test;

my_seq seq;

virtual task run_phase(uvm_phase phase);

super.run_phase(phase);

seq = my_seq::type_id::creat("seq");

seq.start(null);

endtask

endclass

initial begin

CLK = 0;

forever begin

#5 CLK <= ~CLK;

end

end

my_if mif (.*);

assign mif.CLK = CLK;

initial begin

uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env*", "vif", mif);

end

initial begin

run_test();

end

endmodule

*********************

How can I specify the register sequence (extended from "uvm_reg_sequence") as default sequence?

Generally, UVM user guide shows example to use "start()".

But, I want to use "uvm_config_db#(uvm_object_wrapper)::set(this, "xxxxx", "default_sequence", my_seq::type_id::get());"

I don't know what is specified in "xxxxx".

Thanks & Regards,

yyn

Edited June 28, 2011 by yyn

[janick]

Note that this issue is not specific to register sequences but to all sequences in general.

Because this is a virtual sequence that is executed without a sequencer (seq.start(null)), there is not context for the sequence's configuration because sequences can only have sequencers as parents, not any uvm_component (in addition, you fail to specify 'this' in the create() call -- but it would not have worked anyway).

Two options:

1) assign the virtual interface in the component that starts the sequence:

seq.my_seq::type_id::creat("seq");

uvm_config_db#(virtual my_if)::get(this, "", "vif", mif);

seq.vif = mif;

seq.start(null);

2) Execute the sequence on a virtual sequencer and use parent sequencer as the configuration context

seq.my_seq::type_id::creat("seq");

seq.start(sqr);

virtual task body();

uvm_config_db#(virtual my_if)::get(get_parent_sequencer(), "*", "vif", vif);

repeat (10) @(posedge vif.CLK);

endtask