pradeey Posted July 15, 2011 Report Share Posted July 15, 2011 My requirement is that based on the master's request (master is the DUT), I have to generate response from the slave (ie., TB). The response generated could be random or directed. With the code mentioned below in apb example, I tried to generate a random response always from the test bench. class apb_monitor extends uvm_monitor; ... uvm_blocking_peek_imp#(apb_transfer, apb_monitor) addr_trans_export; ... task apb_monitor::run_phase(uvm_phase phase); forever begin // start collecting a transaction - when the address phase is complete -> trans_addr_grabbed; ... end endtask : run_phase task apb_monitor::peek(output apb_transfer trans); @(trans_addr_grabbed) trans = trans_collected; endtask // Now your sequencer has a port so the sequences can access the data from the monitor class apb_slave_sequencer extends uvm_sequencer #(apb_transfer); uvm_blocking_peek_port#(apb_transfer) addr_trans_port; ... endclass class simple_response_seq extends uvm_sequence #(apb_transfer); function new(...); `uvm_object_utils(simple_response_seq) `uvm_declare_p_sequencer(apb_slave_sequencer) // allows your sequence to look at his parent sequencer apb_transfer util_transfer; virtual task body(); forever begin p_sequencer.addr_trans_port.peek(util_transfer); // waits until it sees a valid address on the bus `uvm_do(req); //always random req end endtask // connection between a bus monitor and the sequencer is done in the connect phase of the env: function void apb_env::connect_phase(uvm_phase phase); .. foreach(slaves) if (slaves.is_active == UVM_ACTIVE) slaves.sequencer.addr_trans_port.connect(bus_monitor.addr_trans_export); But the question is how can I control the response from the test case, say, if I want to provide a directed response for a particular transaction? Can you please provide me your inputs on this? Quote Link to comment Share on other sites More sharing options...
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