How to run multiple tests

[qwerty123]

Can we run multiple test in and environment.

If yes then how to do that?

[uwes]

hi,

depends what you mean with "multiple tests":

- running multiple sequences concatinated? this is simple, basically you would do something like: config-seq1; test-seq1; config-seq2; test-seq2;.....

- you may select different tests with the same compiled snapshot without reinvoking compilation/elaboration: so you simply change the +UVM_TESTNAME=arg to select your test.

- you may use the phasing system to concatinate tests: basically you jump back to a previous phase such as reset/pre_reset/configure or similar once a particular test phase has finished. for that you need to build a test controller which controls the sequence of your tests and controls the phasing. typically this is not a really good use model because if you got something to debug in the n'th test you might be required to run the (n-1) upfront to get the same behaviour. also the phasing system does NOT allow you to go back to a phase state earlier than (including?) start_of_simulation once you passed that stage. this restriction prevents you from rebuilding the component hierarchy.

- you can probably use the simulator commands/tcl to reset a simulation and restart it with a new test. this simply allows you to skip simulator invocation time.

- you could probably also use a simulator snapshot capability to run a test till a certain point (post long time config), create a snapshot, reseed some components, run a test, reload snapshot and go with a reseed ..., this allows you to run the same test multiple times with different seeds from a custom timepoint.

- running multiple tests in parallel: if your tests are "sequences" and are not colliding you can run them in parallel. say, in a subsystem you may excercise component A and component B at the same time (even if you had before only A&B tested standalone)

/uwe

[adielkhan]

Hi,

The answer is yes and no.

1) Yes: you can create each test as a top-level sequence and then execute the top-level sequences one-after the other. Issuing a DUT-reset at the start of the top-level-sequences.

2) Yes: you can use phase-rollback to rollback to the pre-reset phase and it will then continue to execute from there. You will need to keep track of how many times you have rolled back and which tests to execute each time. Or you might end up in a bad loop.

3) No: UVM doesn't (yet) officially support testcase concatenation methodology as per other well-known methodologies out there.

For proper testcase concatenation support we need to define which phase the rollback happens to, how we handle seeds-per-test and how we dump coverage-per-test.

Also, there needs to be a defined cleanup action to ensure next testcase is not using something unexpected from previous testcase.

i.e if I run 10-tests without exiting simulation and test=10 fails then I should be able to reproduce test=10 without having to rerun tests=1-9 .

That means that test=10 coverage is bad but test=1:9 coverage is good and should be stored/reported accordingly.

Then you need the UVM to know what to do when it sees +UVM_TESTNAME=test1+test2+test3 etc.

Currently, its probably all possible with some manual effort (after all UVM is just SV code) but the way one person does testcase concatenation might not be the same as the next person thereby making it non-standard.

UVM testcase concatenation is one of the features on the UVM requirements (ID=6.0).

If you think it is useful to your company please ensure you vote on the UVM req-spreadsheet (or voice you opinion loudly).

thanks,

Adiel.