mwhite_cp Posted March 27, 2012 Report Share Posted March 27, 2012 I am trying to do backdoor access to an internal memory but the tool generated errors because hdl_path is not correct for the memory model and it can't find the memory array index. I am using a memory library provided by Xilinx. Could UVM perform backdoor access to the Xilinx or vendor generated Verilog memory model? Thanks! Quote Link to comment Share on other sites More sharing options...
ericswa Posted March 27, 2012 Report Share Posted March 27, 2012 I believe backdoor accesses to vendors' memories (block RAMs) are possible, but require custom read/write tasks. I'm having the same difficulty in VMM RAL, and the RAL user guide discusses only memories that are implemented as one-dimensional arrays (e.g, my_reg[256] ). It has no discussion on backdoors for registers that are inside block RAMs. Quote Link to comment Share on other sites More sharing options...
janick Posted March 27, 2012 Report Share Posted March 27, 2012 You need to define a user-defined backdoor access by extending the uvm_reg_backdoor class and implementing the read() and write() method to access the vendor model as required. Then register an instance of that class with the corresponding memory using the uvm_mem::set_backdoor() method. VMM RAL works the same way. Quote Link to comment Share on other sites More sharing options...
mwhite_cp Posted March 27, 2012 Author Report Share Posted March 27, 2012 Thank you for the responses, it makes sense. Quote Link to comment Share on other sites More sharing options...
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