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How to pass information between two agents?

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My DUT has two interfaces. They are connected to different agents (agentA and agentB). The agentA will generate request to ask DUT to generate several data, then agentB will read it back.

My question is how could I pass the number_of_gen_data from agentA's sequence_item to agentB's sequence_item for agentB to get right number of generated data?

Or I should use other way instead of control agentB's sequnce_item?


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You should use a virtual sequence that generates the number of data items to send/receive and have that sequence control the sequences running on the two agents. If that won't work for you, you'll need to provide a lot more details about the relationship between the two agents.

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Tried virtual sequence according to the example from verification academy. It works. But I met a scope problem with same variable name during try it.

For example:

1. I defined "rand int unsiged number_of_samples" in my sample_transaction extends uvm_sequence_item)

2. I defined the sample variable "rand int unsigned number_of_samples" in my sample_base_seq extends uvm_sequence#(sampel_transaction)

3. I try to use "`uvm_do_with(req, {req.number_of_samples == number_of_samples;})" in sample_base_seq

4. I random the number_of_samples in virtual_seq extends uvm_sequence #(uvm_sequence_item) in this way:

task body():

sample_base_seq sampel_seq;

sample_req = sample_base_seq::type_id::create("sample_req");

sample_req.randomize() with {number_of_samples inside { [2:5];};

sample_req.start(sample_port, this);


The sample_req.number_of_samples is generated properly (all the value hit in 2~5). But the sequence item pass to the driver is not, i got random number_of_samples value outside range [2:5].

If I change the name "number_of_samples" in the sample_base_seq to other name, it works great.

I think it may be the scope issue that the simulator can't get the proper value for the "`uvm_do_with()". But I can't figure out what's wrong I did in my source code.

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You should understand that `uvm_do_with(req, {req.number_of_samples == number_of_samples;})" generates

req.randomize() with {req.number_of_samples == number_of_samples;});

SystemVerilog first searches the object being randomized for all operands inclosed by the with constraint, which in this case is req. So you effectively get

req.req.number_of_samples == req.number_of_samples

since there is no req.req.number_of_samples, randomize() then searches the local scope, the scope containing the randomize statement.

req.number_of_samples == req.number_of_samples, which is a no-op constraint.

What you probably want to do is write

req.randomize() with {number_of_samples == local::number_of_samples;});

The local prefix says you want to only search the local scope, not the object being randomized.

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