[ubus example] is there a redundant uvm_config_db::get in ubus_env? (num_masters)

[SeanChou]

As title, there seems to be 2 redundant lines in ubus_en.sv. line 74 and 86. uvm_config_db::get num_slaves and num_masters.

Although its not harmful, however, it misleads some new comers. if they are really redundant code, hope they could be removed.

[Roman]

In the UVM1.1/a Release's ubus example, "uvm_config_db::get num_slaves and num_masters." are used to factory the multiple masters and slaves agents as high layer scenarios required.

In ubus_env.sv

void'(uvm_config_db#(int)::get(this, "", "num_masters", num_masters));

masters = new[num_masters];

for(int i = 0; i < num_masters; i++) begin

$sformat(inst_name, "masters[%0d]", i);

masters = ubus_master_agent::type_id::create(inst_name, this);

void'(uvm_config_db#(int)::set(this,{inst_name,".monitor"},

"master_id", i));

void'(uvm_config_db#(int)::set(this,{inst_name,".driver"},

"master_id", i));

end

void'(uvm_config_db#(int)::get(this, "", "num_slaves", num_slaves));

slaves = new[num_slaves];

for(int i = 0; i < num_slaves; i++) begin

$sformat(inst_name, "slaves[%0d]", i);

slaves = ubus_slave_agent::type_id::create(inst_name, this);

end

in the test_lib.sv

// 2 Master, 4 Slave test

class test_2m_4s extends ubus_example_base_test;

`uvm_component_utils(test_2m_4s)

function new(string name = "test_2m_4s", uvm_component parent=null);

super.new(name,parent);

endfunction : new

virtual function void build_phase(uvm_phase phase);

loop_read_modify_write_seq lrmw_seq;

begin

// Overides to the ubus_example_tb build_phase()

// Set the topology to 2 masters, 4 slaves

uvm_config_db#(int)::set(this,"ubus_example_tb0.ubus0",

"num_masters", 2);

uvm_config_db#(int)::set(this,"ubus_example_tb0.ubus0",

"num_slaves", 4);

// Control the number of RMW loops

uvm_config_db#(int)::set(this,"ubus_example_tb0.ubus0.masters[0].sequencer.loop_read_modify_write_seq", "itr", 6);

uvm_config_db#(int)::set(this,"ubus_example_tb0.ubus0.masters[1].sequencer.loop_read_modify_write_seq", "itr", 8);

// Define the sequences to run in the run phase

uvm_config_db#(uvm_object_wrapper)::set(this,"*.ubus0.masters[0].sequencer.main_phase",

"default_sequence",

loop_read_modify_write_seq::type_id::get());

lrmw_seq = loop_read_modify_write_seq::type_id::create();

uvm_config_db#(uvm_sequence_base)::set(this,

"ubus_example_tb0.ubus0.masters[1].sequencer.main_phase",

"default_sequence",

lrmw_seq);

for(int i = 0; i < 4; i++) begin

string slname;

$swrite(slname,"ubus_example_tb0.ubus0.slaves[%0d].sequencer", i);

uvm_config_db#(uvm_object_wrapper)::set(this, {slname,".run_phase"},

"default_sequence",

slave_memory_seq::type_id::get());

end

// Create the tb

super.build_phase(phase);

end

endfunction : build_phase

[SeanChou]

Yes, you are right. However, since uvm_component::build() already did get for user, that why the result will be the same if you remove these 2 gets.

Edited April 18, 2012 by SeanChou

[Roman]

Yes. I think this *get* just wants to give user an example for uvm_config_db*set/get explicit usage in ubus example, but uvm factory already did as implicit way.

For new user , they need understand both ways in this example.

This is why it didn't judge whether the uvm_config_db::get is successful or not, like "if(!uvm_config_db)". It just used "void'*" here.

void'(uvm_config_db#(int)::get(this, "", "num_masters", num_masters));

[SeanChou]

yes you are right and this "get" feature is also illustrated by getting the vif between lines nearby in the same file (ubus_env.sv). what I want to address is some member writes many redundant code in his project just because he misleaded by this example and is not aware that factory did this already.

[Roman]

Agree! I think the beginner will make very clear after reading this thread.