virtual sequece or virtual sequencer

[shail]

I have been debating internally whether to use legacy virtual sequencer concept or use the virtual sequence concept.

Any upside- or downside in using one over the other in terms of vertical reuse ?

[Roman]

Hi Shail,

For example :

One DUT which is including the AHB master port, Apb slave port(for register accessing), Physical PAD port (for the specific protocol).

On block level:

in virtual sequencer, you may need at least three seqr(ahb_s_seqr, apb_m_seqr, phy_driver_seqr)

in virtual sequence , you may create multiple Scenario testcases here.

On the Soc level:

Your DUT will be integrated into the system bus(ahb,apb,axi , etc)

for virtual sequencer.

ahb_s_seqr will be replaced by real memory controller(DDR or RAM ...) with the specific Memory model.

APB is commonly translated from AXI/AHB to apb Fabric, ARM(Supposed you choose the ARM) UVC will drive all registers' accessing. ARM seqr(or other module which could access the register, for example DAP port, test port......, you also need create such seqrs in Soc) will take this working in SOC

So ahb_s_seqr and apb_m_seqr will be removed when creating Soc_vseqr.

The phy_driver_seqr will be kept in Soc_vseqr.

For virtual sequence.

On the Soc level, you may create more complex Scenario which is included more DUTs.

So you could reuse the module level's virtual sequence concept into Soc level virtual sequence concept via layering sequence concept.

At last, you need create reusable system cfg object to make “knobs” in Tb building or layering sequences.

Then you will make vertical reuse happen.

Edited March 2, 2012 by Roman